Electronic devices including dielectric layers with different densities of titanium

Abstract

Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

1 . An electronic device comprising: 
 a first electrode;    a dielectric oxide layer on the first electrode wherein the dielectric oxide layer includes titanium, wherein a first portion of the dielectric oxide layer adjacent the first electrode has a first density of titanium, and wherein a second portion of the dielectric oxide layer opposite the first electrode has a second density of titanium different than the first density; and    a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes.    
   
   
       2 . An electronic device according to  claim 1  wherein the dielectric oxide layer further includes tantalum.  
   
   
       3 . An electronic device according to  claim 1  wherein the dielectric oxide layer comprises tantalum titanium oxide.  
   
   
       4 . An electronic device according to  claim 1  further comprising a substrate on the first electrode so that the first electrode is between the substrate and the dielectric oxide layer  
   
   
       5 . An electronic device according to  claim 1  wherein the first density of titanium is greater than the second density of titanium.  
   
   
       6 . An electronic device according to  claim 5  wherein the first density of titanium is in the range of approximately 0.1 to 15 percent.  
   
   
       7 . An electronic device according to  claim 5  wherein the second density of titanium is in the range of approximately 0.001 to 3 percent.  
   
   
       8 . An electronic device according to  claim 1  wherein the first density of titanium is less than the second density of titanium.  
   
   
       9 . An electronic device according to  claim 8  wherein the first density of titanium is in the range of approximately 0.1 to 15 percent.  
   
   
       10 . An electronic device according to  claim 8  wherein the second density of titanium is in the range of approximately 10 to 20 percent.  
   
   
       11 . An electronic device according to  claim 1  wherein each of the first and second electrodes comprises at least one of doped polysilicon, metal, metal oxide, metal nitride, and/or metal oxynitride.  
   
   
       12 . An electronic device according to  claim 1  further comprising a reaction suppressing layer between the first electrode and the dielectric layer.  
   
   
       13 . An electronic device according to  claim 12  wherein the reaction suppressing layer comprises at least one of silicon nitride, silicon oxide, and/or silicon oxynitride.  
   
   
       14 . An electronic device comprising: 
 a first electrode;    a reaction suppressing layer on the first electrode;    a dielectric oxide layer on the reaction suppressing layer so that the reaction suppressing layer is between the first electrode and the dielectric oxide layer and wherein the dielectric oxide layer includes titanium; and    a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the reaction suppressing layer and the second electrode.    
   
   
       15 . An electronic device according to  claim 14  wherein the reaction suppressing layer comprises at least one of silicon nitride, silicon oxide, and/or silicon oxynitride.  
   
   
       16 . An electronic device according to  claim 14  wherein the dielectric oxide layer further includes tantalum.  
   
   
       17 . An electronic device according to  claim 14  wherein the dielectric oxide layer comprises tantalum titanium oxide.  
   
   
       18 . An electronic device according to  claim 14  further comprising a substrate on the first electrode so that the first electrode is between the substrate and the reaction suppressing layer.  
   
   
       19 . An electronic device according to  claim 14  wherein a first portion of the dielectric oxide layer adjacent the reaction suppressing layer has a first density of titanium, and wherein a second portion of the dielectric oxide layer opposite the reaction suppressing layer has a second density of titanium different than the first density.  
   
   
       20 . An electronic device according to  claim 19  wherein the first density of titanium is greater than the second density of titanium.  
   
   
       21 . An electronic device according to  claim 20  wherein the first density of titanium is in the range of approximately 0.1 to 15 percent.  
   
   
       22 . An electronic device according to  claim 20  wherein the second density of titanium is in the range of approximately 0.001 to 3 percent.  
   
   
       23 . An electronic device according to  claim 19  wherein the first density of titanium is less than the second density of titanium.  
   
   
       24 . An electronic device according to  claim 23  wherein the first density of titanium is in the range of approximately 0.1 to 15 percent.  
   
   
       25 . An electronic device according to  claim 23  wherein the second density of titanium is in the range of approximately 10 to 20 percent.  
   
   
       26 . An electronic device according to  claim 14  wherein each of the first and second electrodes comprises at least one of doped polysilicon, metal, metal oxide, metal nitride, and/or metal oxynitride.  
   
   
       27 . A semiconductor memory device comprising: 
 a semiconductor substrate;    a lower electrode formed on the semiconductor substrate;    a dielectric layer which is an oxide film including titanium and tantalum, on an upper surface of the lower electrode; and    an upper electrode on an upper surface of the dielectric layer,    wherein the density of titanium in the dielectric layer depends on the thickness of the dielectric layer.    
   
   
       28 . The semiconductor memory device of  claim 27 , wherein the density of titanium of an area of the dielectric layer adjacent to the lower electrode is 0.1 to 15 percent.  
   
   
       29 . The semiconductor memory device of  claim 27 , wherein a reaction suppressing layer is further interposed between the lower electrode and the dielectric layer so as to prevent a reaction between the lower electrode and the dielectric layer.  
   
   
       30 . The semiconductor memory device of  claim 29 , wherein the reaction suppressing layer is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.  
   
   
       31 . The semiconductor memory device of  claim 27 , wherein the lower electrode and the upper electrode are formed of at least one conductive film selected from a doped polysilicon film, a metal film, a metal oxide film, a metal nitride film, and a metal oxynitride.  
   
   
       32 . A semiconductor memory device comprising: 
 a semiconductor substrate;    a lower electrode formed on the semiconductor substrate;    a reaction suppressing layer formed on an upper surface of the lower electrode;    a first tantalum titanium oxide film formed on an upper surface of the reaction suppressing layer;    a second tantalum titanium oxide film formed on an upper surface of the first tantalum titanium oxide film; and    an upper electrode formed on an upper surface of the second tantalum titanium oxide film,    wherein the density of titanium of the first tantalum titanium oxide film is 0.1 to 15 percent and the density of titanium of the second tantalum titanium oxide film is higher than or equal to the density of titanium of the first tantalum titanium oxide film.    
   
   
       33 . The semiconductor memory device of  claim 32 , wherein the density of titanium of the second tantalum titanium oxide film is 0.001 to 3 percent.  
   
   
       34 . The semiconductor memory device of  claim 32 , wherein the density of titanium of the second tantalum titanium oxide film is 10 to 20 percent.  
   
   
       35 . The semiconductor memory device of  claim 32 , wherein the reaction suppressing layer is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.  
   
   
       36 . The semiconductor memory device of  claim 32 , wherein the lower electrode and the upper electrode are formed of at least one conductive film selected from a doped polysilicon film, a metal film, a metal oxide film, a metal nitride film, and a metal oxynitride.  
   
   
       37 . A dielectric layer for an electronic device, the dielectric layer comprising: 
 a dielectric oxide layer including titanium wherein a first portion of the dielectric oxide layer has a first density of titanium and wherein a second portion of the dielectric oxide layer has a second density of titanium different than the first density.    
   
   
       38 . A dielectric layer according to  claim 37  wherein the dielectric oxide layer further includes tantalum.  
   
   
       39 . A dielectric layer according to  claim 37  wherein the dielectric oxide layer comprises tantalum titanium oxide.