Damascene processing using dielectric barrier films

Abstract

Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid misalignment problems. Embodiments further include dual damascene processing using Cu metallization.

1 - 12 . (canceled)  
     
     
         13 . A semiconductor device comprising: 
 a lower metal feature, comprising copper (Cu) or a Cu alloy, formed in an opening defined by side surfaces of a first dielectric layer having a first barrier layer, comprising a first dielectric barrier material, thereon;    a first barrier liner, comprising a second dielectric barrier material different from the first dielectric barrier material, on the side surfaces of the first dielectric layer between the lower metal feature and the first dielectric layer, the first barrier liner having an upper surface extending to a distance below an upper surface of the first dielectric layer.    
     
     
         14 . The semiconductor device according to  claim 13 , wherein the distance between the upper surface of the first barrier liner and the upper surface of the first barrier layer is about 25 Å to about 200 Å.  
     
     
         15 . The semiconductor device according to  claim 13 , further comprising: 
 a second barrier layer, comprising a third dielectric barrier material different from the first dielectric barrier material, on the first barrier layer overlying the first dielectric layer; and    a dual damascene structure formed on and electrically connected to the lower metal feature, the dual damascene structure comprising:    a second dielectric layer on the second barrier layer;    a third barrier layer, comprising a fourth dielectric barrier material, on the second dielectric layer;    a third dielectric layer on the third barrier layer;    a fourth barrier layer, comprising a fifth dielectric barrier layer material, on the third dielectric layer;    a dual damascene opening comprising a trench, defined by side surfaces of the third dielectric layer, connected to a via hole, defined by side surfaces of the second dielectric layer and a bottom on at least a portion of the upper surface of the lower metal feature;    a second barrier liner, comprising a sixth dielectric barrier material different from the first, fourth and fifth dielectric barrier materials, on the side surfaces of the second dielectric layer defining the via hole and on the side surfaces of the third dielectric layer defining the trench; and    Cu or a Cu alloy filling the dual damascene opening and forming a Cu or Cu alloy line in the third dielectric layer connected to a via in the second dielectric layer which, in turn, is electrically connected to the lower metal feature.    
     
     
         16 . The semiconductor device according to  claim 15 , wherein: 
 an upper surface of the second barrier liner on the side surfaces of the second dielectric layer extends to a distance below the upper surface of the third barrier layer; and    an upper surface of the second barrier liner on the side surfaces of the third dielectric layer extends to a distance below the upper surface of the fourth barrier layer.    
     
     
         17 . The semiconductor device according to  claim 16 , wherein: 
 the distance between the upper surface of the second barrier liner on the side surfaces of the second dielectric layer and the upper surface of the third barrier layer is about 25 Å to about 200 Å; and    the distance between the upper surface of the second barrier liner on the side surfaces of the third dielectric layer and the upper surface of the fourth barrier layer is about 25 Å to about 200 Å.    
     
     
         18 . The semiconductor device according to  claim 15 , wherein the dual damascene opening is misaligned with respect to the lower metal feature such that the bottom of the via hole is on a portion of the upper surface of the lower metal feature and on a portion of an upper surface of the first barrier layer.  
     
     
         19 . The semiconductor device according to  claim 15 , wherein the first and second barrier liners and the first, second, third and fourth barrier layers each have a thickness of about 50 Å to about 500 Å.  
     
     
         20 . The semiconductor device according to  claim 15 , wherein the first, second, third, fourth, fifth and sixth dielectric barrier materials are selected from the group consisting of silicon nitride, silicon carbide and silicon oxynitride.  
     
     
         21 .- 26 . (canceled)  
     
     
         27 . A semiconductor device comprising: 
 a single first dielectric layer overlying a substrate;    a first barrier layer, comprising a first dielectric barrier material, on the single first dielectric layer with an interface therebetween,    a single opening entirely within and defined by side surfaces of the single first dielectric layer and a bottom;    a second barrier layer, comprising a second dielectric barrier material different from the first dielectric barrier material, lining the side surfaces of the single first dielectric layer defining the single opening forming a first barrier liner; and    a conductive material filling the single opening.    
     
     
         28 . The semiconductor device according to  claim 27 , wherein the second barrier layer is not formed on the bottom of the single opening.  
     
     
         29 . The semiconductor device according to  claim 28 , wherein the bottom of the single opening overlies a conductive feature.  
     
     
         30 . The semiconductor device according to  claim 29 , wherein the conductive material is in electrical contact with the conductive feature.  
     
     
         31 . The semiconductor device according to  claim 27 , wherein the first and second dielectric barrier materials are selected from the group consisting of silicon nitride, silicon oxynitride and silicon carbide.  
     
     
         32 . The semiconductor device according to  claim 27 , wherein each of the first and second barrier layers has a thickness of about 50 Å to about 500 Å.  
     
     
         33 . The semiconductor device according to  claim 27 , wherein the conductive material comprises a metal.  
     
     
         34 . The semiconductor device according to  claim 33 , wherein the metal comprises copper (Cu) or a Cu alloy.  
     
     
         35 . The semiconductor device according to  claim 27 , wherein, the first barrier liner has an upper surface extending to a distance below an upper surface of the first dielectric layer.  
     
     
         36 . The semiconductor device according to  claim 35 , wherein the distance between the upper surface of the first barrier liner and the upper surface of the first barrier layer is about 25 Å to about 200 Å.  
     
     
         37 . The semiconductor device according to  claim 27 , wherein the filled opening comprises a lower metal feature, the semiconductor device further comprising: 
 a second barrier layer, comprising a third dielectric barrier material different from the first dielectric barrier material, on the first barrier layer overlying the first dielectric layer; and    a dual damascene structure formed on and electrically connected to the lower metal feature, the dual damascene structure comprising: 
 a second dielectric layer on the second barrier layer;  
 a third barrier layer, comprising a fourth dielectric barrier material, on the second dielectric layer;  
 a third dielectric layer on the third barrier layer;  
 a fourth barrier layer, comprising a fifth dielectric barrier layer material, on the third dielectric layer;  
 a dual damascene opening comprising a trench, defined by side surfaces of the third dielectric layer, connected to a via hole, defined by side surfaces of the second dielectric layer and a bottom on at least a portion of the upper surface of the lower metal feature;  
 a second barrier liner, comprising a sixth dielectric barrier material different from the first, fourth and fifth dielectric barrier materials, on the side surfaces of the second dielectric layer defining the via hole and on the side surfaces of the third dielectric layer defining the trench; and  
 Cu or a Cu alloy filling the dual damascene opening and forming a Cu or Cu alloy line in the third dielectric layer connected to a via in the second dielectric layer which, in turn, is electrically connected to the lower metal feature.  
   
     
     
         38 . The semiconductor device according to  claim 37 , wherein: 
 an upper surface of the second barrier liner on the side surfaces of the second dielectric layer extends to a distance below the upper surface of the third barrier layer; and    an upper surface of the second barrier liner on the side surfaces of the third dielectric layer extends to a distance below the upper surface of the fourth barrier layer.