Dense arrays and charge storage devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

1 . An array of nonvolatile memory cells, wherein each memory cell comprises a semiconductor device and each memory cell size per bit is about (2 f 2 )/N, where f is a minimum feature size and N is a number of device layers in a third dimension, and where N≧1.  
     
     
         2 . The array of  claim 1 , wherein: 
 the array comprises a monolithic three dimensional memory array, comprising a plurality of vertically separated device levels, where N>1; and    the semiconductor device comprises a TFT EEPROM comprising a channel, source and drain regions, and a charge storage region.    
     
     
         3 . The array of  claim 2 , further comprising: 
 a plurality of bit line columns in each device level, each bit line contacting the source or the drain regions of the TFT EEPROMs, and the columns of the bit lines extending substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs;    a plurality of word line rows in each device level, and the rows of the words lines extending substantially parallel to the source-channel-drain direction of the TFT EEPROMs; and    at least one interlayer insulating layer located between the device levels.    
     
     
         4 . The array of  claim 3 , wherein: 
 the TFT EEPROMs further comprise control gates; and    the plurality of word lines are self aligned to the control gates of the respective TFT EEPROMs, to the channel regions of the respective TFT EEPROMs, and to the charge storage regions of the respective TFT EEPROMs located below the respective word lines.    
     
     
         5 . The array of  claim 4 , wherein the TFT EEPROMs further comprise: 
 sidewall spacers located adjacent to sidewalls of the gates of the TFT EEPROMs, wherein the sidewall spacers have approximately the same height as the gates; and    an intergate insulating layer which is located between the sidewall spacers, and above the source and the drain regions of the TFT EEPROMs in each device layer, and wherein the intergate insulating layer has approximately the same height as the sidewall spacers.    
     
     
         6 . The array of  claim 5 , wherein: 
 the word lines are located on the sidewall spacers and on the intergate insulating layer in each device level; and    the word lines contact the respective TFT EEPROM control gates through an opening between the sidewall spacers.    
     
     
         7 . The array of  claim 3 , wherein the TFT EEPROMs further comprise: 
 floating gates located in the charge storage regions; 
 sidewall spacers located adjacent to sidewalls of the floating gates of the TFT EEPROMs; and  
 an intergate insulating layer which is located between the sidewall spacers, and above the source and the drain regions of the TFT EEPROMs in each device layer, and wherein the intergate insulating layer has approximately the same height as the sidewall spacers; and  
 a control gate dielectric located above the sidewall spacers and the intergate insulating layer and below the word lines.  
   
     
     
         8 . The array of  claim 7 , wherein the floating gates extend vertically and laterally above the sidewall spacers, such that the floating gates have a “T” shape.  
     
     
         9 . The array of  claim 3 , further comprising word line contacts and bit line contacts which connect the word lines and the bit lines with peripheral circuits located in a semiconductor substrate below the first device level of the array; and 
 wherein the bit line contacts extend between plural device layers.