Semiconductor device and method for fabricating the same

Abstract

A semiconductor device including an n-channel MISFET including source/drain regions 38 formed in a semiconductor substrate 10 with a channel region between them, and a gate electrode 44 of a metal silicide formed over the channel region with a gate insulating film 12 interposed therebetween; and an insulating film 46 formed over the gate electrode 44 from side walls of the gate electrode 44 to an upper surface of the gate electrode 44 , having a tensile stress from 1.0 to 2.0 GPa and applying the tensile stress to the channel region.

1 . A semiconductor device comprising: 
 an n-channel MISFET including source/drain regions formed in a semiconductor substrate with a channel region between them, and a first gate electrode of a metal silicide formed over the channel region with a gate insulating film interposed therebetween; and    a first insulating film formed over the first gate electrode from side walls of the first gate electrode to an upper surface of the first gate electrode, having a tensile stress from 1.0 to 2.0 GPa, and said first insulating film applying a tensile stress to the channel region.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein 
 a metal silicide film is formed on the surface of the source/drain regions of the semiconductor substrate.    
     
     
         3 . The semiconductor device according to  claim 1 , wherein 
 the first insulating film comprises silicon nitride.    
     
     
         4 . The semiconductor device according to  claim 1 , further comprising: 
 a second insulating film formed between the semiconductor substrate and the first insulating film and covering the source/drain regions.    
     
     
         5 . The semiconductor device according to  claim 4 , which further comprises 
 another MISFET including a second gate electrode with a gate length longer than a gate length of the first gate electrode, and in which    the second insulating film is formed, extended over said second gate electrode, and    said second gate electrode has a polycrystalline silicon gate structure or a polycide gate structure.    
     
     
         6 . The semiconductor device according to  claim 4 , wherein 
 the second insulating film comprises silicon oxide.    
     
     
         7 . The semiconductor device according to  claim 4 , further comprising: 
 a third insulating film formed between the second insulating film and the first insulating film and extended over said first gate electrode.    
     
     
         8 . A semiconductor device comprising: 
 a p-channel MISFET including source/drain regions in a semiconductor substrate with a channel region between them, and a first gate electrode of a metal silicide formed over the channel region with a gate insulating film interposed therebetween; and    a first insulating film formed over the first gate electrode from side walls of the first gate electrode to an upper surface of the first gate electrode, having a compression stress from 1.0 to 3.0 GPa, and said first insulating film applying a compression stress to the channel region.    
     
     
         9 . The semiconductor device according to  claim 8 , wherein 
 a metal silicide film is formed on the surface of the source/drain regions of the semiconductor substrate.    
     
     
         10 . The semiconductor device according to  claim 8 , wherein 
 the first insulating film comprises silicon nitride.    
     
     
         11 . The semiconductor device according to  claim 8 , further comprising: 
 a second insulating film formed between the semiconductor substrate and the first insulating film and covering the source/drain regions.    
     
     
         12 . The semiconductor device according to  claim 11 , which further comprises 
 another MISFET including a second gate electrode with a gate length longer than a gate length of said first gate electrode, and in which    the second insulating film is formed, extended over said second gate electrode, and    said second gate electrode has a polycrystalline silicon gate structure or a polycide gate structure.    
     
     
         13 . The semiconductor device according to  claim 11 , wherein 
 the second insulating film comprises silicon oxide.    
     
     
         14 . The semiconductor device according to  claim 11 , further comprising: 
 a third insulating film formed between the second insulating film and the first insulating film and extended over said first gate electrode.    
     
     
         15 . A method for fabricating a semiconductor device comprising: 
 forming an n-channel MISFET including source/drain regions formed in a semiconductor substrate with a channel region between them, and a first gate electrode of a polycrystalline silicon formed over the channel region with a gate insulating film interposed therebetween;    forming a first insulating film over the semiconductor substrate and the n-channel MISFET; wherein said first insulating film is formed thin on the first gate electrode and thick on the source/drain regions;    etching the first insulating film, to expose the gate electrode;    substituting the polycrystalline silicon forming the first gate electrode into a metal silicide; and    forming a second insulating film over the first gate electrode from side walls of the first gate electrode to an upper surface of the first gate electrode and having a tensile stress from 1.0 to 2.0 GPa.    
     
     
         16 . The method for fabricating a semiconductor device according to  claim 15 , wherein forming the MISFET comprises: 
 forming the gate insulating film and a polycrystalline silicon film over the semiconductor substrate;    polishing a surface of the polycrystalline silicon film flat; and    patterning the polycrystalline silicon film to form the first gate electrode.    
     
     
         17 . The method for fabricating a semiconductor device according to  claim 15 , further comprising, after forming the MISFET and before forming the first insulating film: 
 forming a metal silicide film on the surface of the source/drain regions of the semiconductor substrate.    
     
     
         18 . The method for fabricating a semiconductor device according to  claim 17 , wherein 
 the metal silicide film is formed also on the first gate electrode.    
     
     
         19 . The method for fabricating a semiconductor device according to  claim 15 , wherein 
 in forming the MISFET, another MISFET including a second gate electrode having a gate length longer than a gate length of the first gate electrode is formed over the semiconductor substrate,    the first insulating film is formed thin on the first gate electrode and thick on the source/drain regions and said second gate electrode, and    the first insulating film is etched, so as to leave the first insulating film on the source/drain regions and said second gate electrode and remove the first insulating film from the first gate electrode.    
     
     
         20 . The method for fabricating a semiconductor device according to  claim 15 , wherein 
 the first insulating film comprises silicon oxide formed by high density plasma CVD or spin coating.    
     
     
         21 . The method for fabricating a semiconductor device according to  claim 15 , wherein 
 in the step of etching the first insulating film, the first insulating film is etched without using a mask.    
     
     
         22 . A method for fabricating a semiconductor device comprising: 
 forming a p-channel MISFET including source/drain regions located in a semiconductor substrate with a channel region between them, and a first gate electrode of a polycrystalline silicon formed over the channel region with a gate insulating film interposed therebetween;    forming a first insulating film over the semiconductor substrate and the p-channel MISFET, wherein said first insulating film is formed thin on the first gate electrode and thick on the source/drain regions;    etching the first insulating film to expose the first gate electrode;    substituting the polycrystalline silicon forming the gate electrode into a metal silicide; and    forming a second insulating film over the first gate electrode substituted into the metal silicide from side walls of the first gate electrode to an upper surface of the first gate electrode and having a compression stress from 1.0 to 3.0 GPa.    
     
     
         23 . The method for fabricating a semiconductor device according to  claim 22 , wherein forming the MISFET comprises: 
 forming the gate insulating film and a polycrystalline silicon film over the semiconductor substrate;    polishing a surface of the polycrystalline silicon film flat; and    patterning the polycrystalline silicon film to form the first gate electrode.    
     
     
         24 . The method for fabricating a semiconductor device according to  claim 22 , further comprising, after forming the MISFET and before forming the first insulating film: 
 forming a metal silicide film on the surface of the source/drain regions of the semiconductor substrate.    
     
     
         25 . The method for fabricating a semiconductor device according to  claim 24 , wherein 
 the metal silicide film is formed also on the first gate electrode.    
     
     
         26 . The method for fabricating a semiconductor device according to  claim 22 , wherein 
 in forming the MISFET, a second MISFET including a second gate electrode with a gate length longer than a gate length of the first gate electrode is formed over the semiconductor substrate,    in forming the first insulating film, the first insulating film is formed thin on the first gate electrode and thick on the source/drain regions and said second gate electrode, and    in etching the first insulating film, the first insulating film is etched so as to leave the first insulating film on the source/drain regions and said second gate electrode, and remove the first insulating film from the first gate electrode.    
     
     
         27 . The method for fabricating a semiconductor device according to  claim 22 , wherein 
 the first insulating film comprises silicon oxide formed by high density plasma CVD or spin coating.    
     
     
         28 . The method for fabricating a semiconductor device according to  claim 22 , wherein 
 the first insulating film is etched without using a mask.