Circuit and Method for Service Clock Recovery

Abstract

A method for controlling a local clock in a node coupled to a packet network is disclosed. The method involves generating a first control signal based on RTS values received during a first period of time and generating at least one additional control signal based on RTS values received during at least one additional period of time. The method further involves selecting one of the first and at least one additional control signals to control the frequency of a local clock.

1 . A circuit for adaptively recovering a clock signal at a network node, comprising: 
 means for incorporating a signal into a plurality of data packets sent to the network node;    means, responsive to the means for incorporating, for determining a rate at which the plurality of data packets are processed in the network node over a plurality of time periods; and    means, coupled to the means for determining and responsive to the means for incorporating, for substantially synchronizing the rate with a local service clock such that the clock signal is substantially free of jitter.    
   
   
       2 . The circuit of  claim 1 , wherein the means for incorporating a signal into the plurality of data packets sent to the network node includes a circuit that generates residual time stamp values.  
   
   
       3 . The circuit of  claim 1 , wherein the means for determining the rate at which the plurality of data packets are processed over the plurality of time periods includes: 
 a buffer, adapted to receive the plurality of data packets;    a reassembler, coupled to the buffer, and adapted to determine a maximum fill level of the buffer; and    an oscillator, adapted to output the local service clock based on a relative maximum fill level.    
   
   
       4 . The circuit of  claim 1 , wherein the means for substantially synchronizing the clock rate with the service clock plurality of data packets to provide acceptable circuit emulation service includes a processor adapted to calculate cell delay variation.  
   
   
       5 . The circuit of  claim 4 , wherein the processor is one of a field programmable gate array and a microprocessor.  
   
   
       6 . A method for controlling a local clock in a node coupled to a packet network, the method comprising: 
 generating a first control signal based on RTS values received during a first period of time;    generating at least one additional control signal based on RTS values received during at least one additional period of time; and    selecting one of the first and at least one additional control signals to control the frequency of a local clock.    
   
   
       7 . A method for service clock recovery, the method comprising: 
 removing RTS values from data packets at a destination node;    using the removed RTS values over a plurality of time periods to set the service clock for the destination node.    
   
   
       8 . The method of  claim 7 , and further using buffer fill levels to control the local service clock.  
   
   
       9 . A method for adaptive clock recovery, the method comprising: 
 monitoring a buffer fill level for a plurality of time periods;    identifying a relative maximum fill level during the plurality of time periods; and    controlling the frequency of a recovered clock signal based on the relative maximum fill levels for the plurality of time periods such that the recovered clock signal is substantially free of jitter.    
   
   
       10 . The method of  claim 9 , wherein controlling the frequency of the recovered clock signal comprises: 
 comparing calculations for the control value for a longest of the plurality of time periods with the control values for the other of the plurality of time periods; and    selecting the control value for the longest of the plurality of time periods unless one of the control values of the other of the plurality of time periods is not within selected bounds of the control value of the longest of the plurality of time periods.    
   
   
       11 . A method for recovering a clock at a destination node, the method comprising: 
 receiving data packets at the destination node;    calculating control values for a numerically controlled oscillator over a plurality of time periods; and    selectively using the control values to set the frequency of the numerically controlled oscillator.    
   
   
       12 . The method of  claim 11 , wherein calculating control values comprises calculating control values using a peak buffer fill level for each of the plurality of time periods.  
   
   
       13 . The method of  claim 11 , wherein calculating control values comprises calculating control values using residual time stamp (RTS) values.