Contact etching utilizing partially recessed hard mask

Abstract

A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

1 . A method for forming contact holes using a partially recessed hard mask, comprising: 
 providing a substrate with a device region and an alignment region comprising an opening therein serving as an alignment mark;    forming a dielectric layer overlying the substrate and filling the opening;    forming a polysilicon pattern layer overlying the dielectric layer, acting as the hard mask, wherein the polysilicon pattern layer comprises a recessed region over the opening and a plurality of holes therein on the device region, exposing the underlying dielectric layer; and etching the exposed dielectric layer using the polysilicon pattern layer as an etch mask, forming a plurality of contact holes in the dielectric layer on the device region.    
   
   
       2 . The method as claimed in  claim 1 , wherein formation of the polysilicon pattern layer comprises: 
 forming a polysilicon layer overlying the dielectric layer;    partially etching the polysilicon layer over the opening on the alignment region using a first photoresist pattern layer as a hard mask, forming the recessed region;    removing the first photoresist pattern layer;    etching the polysilicon layer on the device region using a second photoresist pattern layer as a hard mask, forming a plurality of holes therein; and    removing the second photoresist pattern layer.    
   
   
       3 . The method as claimed in  claim 1 , wherein the dielectric layer comprises borophosphosilicate glass or tetraethyl orthosilicate oxide.  
   
   
       4 . The method as claimed in  claim 1 , wherein the polysilicon pattern layer has a thickness of about 700 to 1000 Å.  
   
   
       5 . The method as claimed in  claim 4 , wherein the recessed region has a depth of about 300 to 500 Å.  
   
   
       6 . The method as claimed in  claim 1 , wherein the contact hole comprises a bit line contact hole, a gate contact hole, or a substrate contact hole.  
   
   
       7 . The method as claimed in  claim 1 , further comprising: 
 conformably forming a barrier layer overlying the polysilicon pattern layer and the inner surfaces of the contact holes on the device region and the recessed region on the alignment region;    forming a metal layer on the barrier layer and filling the contact holes and the recessed region; and    planarizing the metal layer.    
   
   
       8 . The method as claimed in  claim 7 , wherein the barrier layer comprises titanium and titanium nitride.  
   
   
       9 . The method as claimed in  claim 7 , wherein the metal layer comprises tungsten.  
   
   
       10 . The panel as claimed in  claim 7 , wherein the metal layer is planarized by chemical mechanical polishing.  
   
   
       11 - 17 . (canceled)