Semiconductor packaging device and manufacture thereof

Abstract

A semiconductor packaging device comprises a carrier having at least a cavity/a slot thereon, at least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second plating through holes therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads.

1 . An interface for chip assembly comprising, 
 a first insulating layer comprising a plurality of first connectors for connecting to a first chip;    a second insulating layer comprising a plurality of second connectors for connecting to a second chip and a plurality of third connectors for connecting to a circuit board; and    a third insulating layer between said first and second insulating layers, comprising a plurality of conductive layout lines for arranging the connection between said first, second, and third connectors.    
   
   
       2 . An interface for chip assembly as claimed in  claim 1 , wherein said first insulating layer is affixed to a carrier which comprises said first chip.  
   
   
       3 . An interface for chip assembly as claimed in  claim 1 , wherein said plurality of first connectors are connecting to said first chip via bonding pads.  
   
   
       4 . An interface for chip assembly as claimed in  claim 1 , wherein said plurality of second connectors are connecting to said second chip via a ball grid array.  
   
   
       5 . An interface for chip assembly as claimed in  claim 1 , wherein said plurality of third connectors are connecting to said circuit board via a ball grid array.  
   
   
       6 . An interface for chip assembly as claimed in  claim 5 , wherein height of said ball grid array is higher than said second chip.