Wafer-level-chip-scale package and method of fabrication

Abstract

A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.

1 . A wafer-level-chip-scale package comprising: 
 a semiconductor substrate comprising an integrated circuit;    a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit; and    a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.    
     
     
         2 . The package of  claim 1 , wherein the protective portion is formed from an epoxy molding compound.  
     
     
         3 . The package of  claim 1 , wherein conductive ball is formed from solder.  
     
     
         4 . The package of  claim 1 , further comprising: 
 a bonding pad disposed on the semiconductor substrate and is electrically connected to the integrated circuit;    a protective layer disposed on edges of the bonding pad and on the semiconductor substrate;    a first insulation layer disposed on the protective layer;    an under barrier metal disposed on the first insulation layer and the bonding pad;    a distribution layer disposed on the under barrier metal;    a second insulation layer disposed on the distribution layer; and    a ball pad disposed on the second insulation layer and adapted to receive the conductive ball.    
     
     
         5 . A method of fabricating a wafer-level-chip-scale package, the method comprising: 
 preparing a wafer comprising a plurality of semiconductor substrates, each semiconductor substrate comprising an integrated circuit and a ball pad connected to the integrated circuit;    attaching a temporary supporting board to a topside of the wafer;    separating the plurality of semiconductor substrates on the temporary supporting board by selectively cutting a backside of the wafer while not cutting through the temporary supporting board;    molding the backside of the wafer with an insulating material;    removing the temporary supporting board;    forming a conductive ball on the topside of the wafer in electrical contact with the ball pad; and    cutting the insulating material to separate the plurality semiconductor substrates.    
     
     
         6 . The method of  claim 5 , wherein the preparing the wafer comprises removing a predetermined thickness from the backside of the wafer following fabrication of the integrated circuit and ball pad.  
     
     
         7 . The method of  claim 5 , further comprising: 
 removing a predetermined thickness of the insulating material following molding the backside of the wafer.    
     
     
         8 . The method of  claim 5 , wherein, the insulating material comprises an epoxy molding compound.  
     
     
         9 . The method of  claim 5 , further comprising: 
 cleaning the topside of the wafer following removal of the temporary supporting board.    
     
     
         10 . The method of  claim 5 , wherein the conductive ball is formed from solder.  
     
     
         11 . The method of  claim 5 , wherein preparing the wafer comprises: 
 for each semiconductor substrate,    fabricating the integrated circuit on the semiconductor substrate and forming the bonding pad in electrical connection with the integrated circuit;    forming a protective layer on edges of the bonding pad and on the semiconductor substrate;    forming a first insulation layer on the protective layer;    forming an under barrier metal on the first insulation layer and the bonding pad;    forming a distribution layer on the under barrier metal;    forming a second insulation layer on distribution layer; and    forming the ball pads on exposed portions of the second insulation layers.