Packaging for high speed integrated circuits

Abstract

An integrated circuit package comprises an integrated circuit die comprising a first pad, a second pad adjacent to the first pad, a third pad adjacent to the second pad, and a fourth pad adjacent to the third pad. A lead frame comprises a first lead, a second lead adjacent to the first lead, a third lead adjacent to the second lead, and a fourth lead adjacent to the third lead, wherein a first end of the fourth lead extends beyond at least one of the first, second, and third leads and in a direction towards a path defined by the third lead. First, second, third and fourth bondwires connecting the first, second, fourth and third leads to the first, second, third and fourth pads, respectively.

1 . An integrated circuit package comprising: 
 an integrated circuit die comprising a first pad, a second pad adjacent to said first pad, a third pad adjacent to said second pad, and a fourth pad adjacent to said third pad;    a lead frame comprising a first lead, a second lead adjacent to said first lead, a third lead adjacent to said second lead, and a fourth lead adjacent to said third lead, wherein a first end of said fourth lead extends beyond at least one of said first, second, and third leads and in a direction towards a path defined by said third lead; and    first, second, third and fourth bondwires connecting said first, second, fourth and third leads to said first, second, third and fourth pads, respectively.    
     
     
         2 . The integrated circuit package of  claim 1  wherein said first lead carries a signal having a first polarity, said second lead carries a signal having a second polarity, said third lead carries a signal having said second polarity and said fourth lead carries a signal having said first polarity, wherein said first and second polarities are opposite polarities.  
     
     
         3 . The integrated circuit package of  claim 1  wherein said leads of said lead frame carry high speed differential signals.  
     
     
         4 . The integrated circuit package of  claim 3  wherein said high speed signals have a frequency greater than or equal to 1 Gigabit per second (Gb/s).  
     
     
         5 . The integrated circuit package of  claim 1  wherein said first, second, third and fourth leads are spaced at least a first distance from said integrated circuit die and said lead frame further comprises fifth and sixth leads that are spaced a second distance from said integrated circuit die, wherein said first distance is greater than said second distance.  
     
     
         6 . The integrated circuit package of  claim 1  further comprising: 
 fifth and sixth leads;    fifth and sixth pads on said integrated circuit die;    fifth and sixth bondwires connecting said fifth and sixth leads to said fifth and sixth pads, wherein said first, second, third and fourth bondwires have a first length and said fifth and sixth bondwires have a second length and wherein said second length is shorter than said first length.    
     
     
         7 . The integrated circuit package of  claim 5  wherein said fifth and sixth leads carry signals having a first speed and wherein said first, second, third and fourth leads carry signals having a second speed that is higher than said first speed.  
     
     
         8 . The integrated circuit package of  claim 1  further comprising a serializer/deserializer (SERDES) module that communicates with said first, second, third and fourth pads.  
     
     
         9 . The integrated circuit die of  claim 8  wherein said first and second pads of said integrated circuit die are associated with differential transmit signals of said SERDES module and said third and fourth pads of said integrated circuit die are associated with differential receive signals of said SERDES module.  
     
     
         10 . A network interface comprising the integrated circuit package of  claim 1 .  
     
     
         11 . The network interface of  claim 10  wherein said network interface is Ethernet compliant and operates at speeds greater than 1 Gigabit per second.  
     
     
         12 . The integrated circuit package of  claim 1  further comprising a fifth pad on said integrated circuit die, wherein said first bondwire comprises first and second bondwires that are stacked and connected between said first lead and said first pad and said fifth pad, respectively, of said integrated circuit die.  
     
     
         13 . The integrated circuit package of  claim 1  wherein said first, second, third and fourth bondwires each comprise first and second stacked bondwires.  
     
     
         14 . A method of providing an integrated circuit package comprising: 
 creating a first pad, a second pad adjacent to said first pad, a third pad adjacent to said second pad, and a fourth pad adjacent to said third pad on an integrated circuit die;    using a lead frame comprising a first lead, a second lead adjacent to said first lead, a third lead adjacent to said second lead, and a fourth lead adjacent to said third lead;    extending a first end of said fourth lead beyond at least one of said first, second, and third leads and in a direction towards a path defined by said third lead; and    providing first, second, third and fourth bondwires connecting said first, second, fourth and third leads to said first, second, third and fourth pads, respectively.    
     
     
         15 . The method of  claim 14  further comprising using said first lead to carry a signal having a first polarity, said second lead to carry a signal having a second polarity, said third lead to carry a signal having said second polarity and said fourth lead to carry a signal having said first polarity, wherein said first and second polarities are opposite polarities.  
     
     
         16 . The method of  claim 14  further comprising using said leads of said lead frame to carry high speed differential signals.  
     
     
         17 . The method of  claim 16  wherein said high speed signals have a frequency greater than or equal to 1 Gigabit per second (Gb/s).  
     
     
         18 . The method of  claim 14  further comprising: 
 spacing said first, second, third and fourth leads at least a first distance from said integrated circuit die; and    providing fifth and sixth leads on said lead frame that are spaced a second distance from said integrated circuit die, wherein said first distance is greater than said second distance.    
     
     
         19 . The method of  claim 14  further comprising: 
 providing fifth and sixth leads;    creating fifth and sixth pads on said integrated circuit die;    connecting said fifth and sixth leads to said fifth and sixth pads using fifth and sixth bondwires, wherein said first, second, third and fourth bondwires have a first length and said fifth and sixth bondwires have a second length and wherein said second length is shorter than said first length.    
     
     
         20 . The method of  claim 18  further comprising: 
 using said fifth and sixth leads to carry signals having a first speed; and    using said first, second, third and fourth leads to carry signals having a second speed that is higher than said first speed.    
     
     
         21 . The method of  claim 14  further comprising: 
 creating a fifth pad on said integrated circuit die;    using first and second stacked bondwires that are stacked and connected between said first lead and said first pad and said fifth pad, respectively, of said integrated circuit die for said first bondwire.    
     
     
         22 . The method of  claim 14  wherein said first, second, third and fourth bondwires each comprise first and second stacked bondwires.  
     
     
         23 . An integrated circuit package comprising: 
 integrated circuit die means for performing a function comprising first connecting means for providing a first connection surface, second connecting means for providing a second connection surface adjacent to said first connecting means, third connecting means for providing a third connection surface adjacent to said second connecting means, and fourth connecting means for providing a fourth connection surface adjacent to said third connecting means;    frame means comprising first conducting means for conducting, second conducting means for conducting adjacent to said first conducting means, third conducting means for conducting adjacent to said second conducting means, and fourth conducting means for conducting adjacent to said third conducting means, wherein a first end of said fourth conducting means extends beyond at least one of said first, second, and third conducting means and in a direction towards a path defined by said third conducting means; and    first, second, third and fourth wire means for connecting said first, second, fourth and third conducting means to said first, second, third and fourth connecting means, respectively.    
     
     
         24 . The integrated circuit package of  claim 23  wherein said first conducting means carries a signal having a first polarity, said second conducting means carries a signal having a second polarity, said third conducting means carries a signal having said second polarity and said fourth conducting means carries a signal having said first polarity, wherein said first and second polarities are opposite polarities.  
     
     
         25 . The integrated circuit package of  claim 23  wherein said conducting means of said frame means carries high speed differential signals.  
     
     
         26 . The integrated circuit package of  claim 25  wherein said high speed signals have a frequency greater than or equal to 1 Gigabit per second (Gb/s).  
     
     
         27 . The integrated circuit package of  claim 23  wherein said first, second, third and fourth conducting means are spaced at least a first distance from said integrated circuit die means and said frame means further comprises fifth and sixth conducting means that are spaced a second distance from said integrated circuit die means, wherein said first distance is greater than said second distance.  
     
     
         28 . The integrated circuit package of  claim 23  further comprising: 
 fifth and sixth conducting means for conducting;    fifth and sixth connecting means for providing a connection surface on said integrated circuit die means;    fifth and sixth wire means for connecting said fifth and sixth conducting means to said fifth and sixth connecting means, wherein said first, second, third and fourth wire means have a first length and said fifth and sixth wire means have a second length and wherein said second length is shorter than said first length.    
     
     
         29 . The integrated circuit package of  claim 27  wherein said fifth and sixth conducting means carry signals having a first speed and wherein said first, second, third and fourth conducting means carry signals having a second speed that is higher than said first speed.  
     
     
         30 . The integrated circuit package of  claim 23  further comprising serializer/deserializer (SERDES) means, that communicates with said first, second, third and fourth connecting means, for serializing and deserializing signals.  
     
     
         31 . The integrated circuit package of  claim 30  wherein said first and second connecting means of said integrated circuit die means are associated with differential transmit signals of said SERDES means and said third and fourth connecting means of said integrated circuit die means are associated with differential receive signals of said SERDES means.  
     
     
         32 . A network interface comprising the integrated circuit package of  claim 23 .  
     
     
         33 . The network interface of  claim 32  wherein said network interface is Ethernet compliant and operates at speeds greater than 1 Gigabit per second.  
     
     
         34 . The integrated circuit package of  claim 23  further comprising fifth connecting means for providing a connection surface on said integrated circuit die means, wherein said first wire means comprises first and second stacked wire means for connecting that are stacked and connected between said first conducting means and said first connecting means and said fifth connecting means, respectively, of said integrated circuit die means.  
     
     
         35 . The integrated circuit package of  claim 23  wherein said first, second, third and fourth wire means each comprise first and second stacked wire means for connecting.