Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor substrate; forming a dielectric layer on the surface of the semiconductor substrate including the isolation trench; filling the isolation trench with a CVD layer; removing the dielectric layer except a portion in the isolation trench by an etching; sequentially forming an insulating layer and a conductive layer; forming a resist defining a pattern which covers via the conductive layer a portion of the insulating layer in contact with the dielectric layer; and performing an anisotropic etching on the resist to thereby remove a portion of the conductive layer exposing a surface thereof.

1 . A semiconductor device, comprising: 
 a semiconductor substrate;    an isolation trench formed inside said semiconductor substrate;    a first layer formed along an inner wall of said isolation trench so as to constitute a lining;    a second layer formed in contact with an inner surface of said first layer so as to fill said isolation trench; and    a conductive layer selectively formed on said isolation trench so as to cover said first layer and said second layer.    
   
   
       2 . The semiconductor device as recited in  claim 1 , further comprising a gate electrode in a region different from said conductive layer, wherein said conductive layer and said gate electrode are formed in a same process.  
   
   
       3 . The semiconductor device as recited in  claim 2 , further comprising an insulating layer over a first region where said conductive layer is provided and a second region where said gate electrode is provided, Wherein said insulating layer insulates said first layer and said second layer in said first region, as well as said gate electrode and said semiconductor substrate in said second region.  
   
   
       4 . The semiconductor device as recited in  claim 1 , wherein said second layer is a CVD layer.  
   
   
       5 . The semiconductor device as recited in  claim 4 , wherein said CVD layer is a polycrystalline silicon layer.  
   
   
       6 . The semiconductor device as recited in  claim 4 , wherein said CVD layer is constituted of a same material as said first layer.  
   
   
       7 . The semiconductor device as recited in  claim 1 , wherein said first layer is a silicon oxide layer.