Semiconductor device and method for fabricating the same

Abstract

In a MIEET, an impurity which changes a lattice constant is introduced into part of a gate electrode located on an isolation region. A stress which is generated in part of the gate electrode as a starting point and improves the mobility of carries is applied to a channel region with the part of the gate electrode.

1 . A semiconductor device comprising: 
 a substrate including an active region formed therein;    an isolation region formed in the substrate so as to surround the active region;    a gate insulation film formed on the active region;    a gate electrode formed on the gate insulation film so as to extend onto the isolation region;    impurity doped regions formed in parts of the active region located in both sides of the gate electrode, respectively, and containing a first impurity having a conductivity type,    wherein the gate electrode includes first part located on the isolation region and second part located on the active region, and    wherein the first part of the gate electrode includes a larger stress than a stress in the second part of the gate electrode.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the first part of the gate electrode contains a second impurity which changes a lattice constant of the gate electrode.  
     
     
         3 . The semiconductor device of  claim 2 , wherein the second part of the gate electrode contains the second impurity at a lower concentration than a concentration of the second impurity in the first part.  
     
     
         4 . The semiconductor device of  claim 2 , wherein the second impurity is an impurity which does not have a conductivity type.  
     
     
         5 . The semiconductor device of  claim 2 , wherein the first impurity is an n-type impurity, and 
 wherein the second impurity is an impurity which increases the lattice constant of the gate electrode.    
     
     
         6 . The semiconductor device of  claim 2 , wherein the gate electrode is formed of polysilicon, and 
 wherein the second impurity is germanium.    
     
     
         7 . The semiconductor device of  claim 2 , wherein the first impurity is an n-type impurity, and 
 wherein the second impurity is an impurity having the same conductivity type as the conductivity type of the first impurity.    
     
     
         8 . The semiconductor device of  claim 2 , wherein the first impurity is a p-type impurity, and 
 wherein the second impurity is an impurity which reduces the lattice constant of the gate electrode.    
     
     
         9 . The semiconductor device of  claim 2 , wherein the gate electrode is formed of polysilicon, and 
 wherein the second impurity is carbon.    
     
     
         10 . The semiconductor device of  claim 1 , further comprising: 
 a dummy gate electrode formed over the substrate so as to face the gate electrode with an associated one of the impurity doped regions interposed between the dummy gate electrode and the gate electrode and containing a third impurity which changes an intrinsic lattice constant of a material forming the dummy gate electrode.    
     
     
         11 . The semiconductor device of  claim 10 , wherein the first impurity is an n-type impurity, and 
 wherein the third impurity is an impurity which reduces the lattice constant of the dummy gate electrode.    
     
     
         12 . The semiconductor device of clam  11 , wherein the dummy gate electrode is formed of polysilicon, and 
 wherein the third impurity is carbon.    
     
     
         13 . The semiconductor device of  claim 10 , wherein the first impurity is a p-type impurity, and 
 wherein the third impurity is an impurity which increases the lattice constant of the dummy gate electrode.    
     
     
         14 . The semiconductor device of  claim 13 , wherein the dummy gate electrode is formed of polysilicon, and 
 wherein the third impurity is germanium or tin.    
     
     
         15 . The semiconductor device of  claim 10 , wherein the third impurity is contained in part of an associated one of the impurity regions located below and on a side of the dummy gate electrode.  
     
     
         16 . The semiconductor device of  claim 10 , wherein the dummy gate electrode is provided over the isolation region and the active region.  
     
     
         17 . A semiconductor device comprising: 
 a substrate including an active region formed therein;    an isolation region formed in the substrate so as to surround the active region;    a gate insulation film formed on the active region;    a gate electrode provided on the gate insulation film;    impurity doped regions formed in parts of the active region located on both sides of the gate electrode, respectively, and containing a first impurity having a conductivity type; and    a dummy gate electrode provided over the substrate so as to face the gate electrode with an associated one of the impurity doped regions interposed between the dummy gate electrode and the gate electrode and containing a second impurity which changes an intrinsic lattice constant of a material forming the dummy gate electrode.    
     
     
         18 . The semiconductor device of  claim 17 , wherein the first impurity is an n-type impurity, and 
 wherein the second impurity is an impurity which reduces the lattice constant of the dummy gate electrode.    
     
     
         19 . The semiconductor device of  claim 17 , wherein the first impurity is a p-type impurity, and 
 wherein the second impurity is an impurity which increases the lattice constant of the dummy gate electrode.    
     
     
         20 . A method for fabricating a semiconductor device, the method comprising the steps of: 
 a) forming an isolation region in a substrate;    b) forming a gate insulation film on an active region formed in part of the substrate surrounded by the isolation region;    c) forming a gate electrode on the gate insulation film so as to extend onto the isolation region;    d) making first part of the gate electrode located on the isolation region contain a larger stress than a stress in second part of the gate electrode located on the active region; and    e) forming impurity doped regions in parts of the active region located on both sides of the gate electrode, respectively, each of the impurity regions containing a first impurity having a conductivity type.    
     
     
         21 . The method of  claim 20 , wherein in the step d), a second impurity which changes a lattice constant of the gate electrode is selectively implanted into the first part of the gate electrode, thereby making the first part include a larger stress than a stress in the second part of the gate electrode.  
     
     
         22 . The method of  claim 21 , wherein in the step c), the second impurity is implanted into the gate electrode patterned at a smaller dose than a dose of the second impurity to be implanted in the step d).  
     
     
         23 . The method of  claim 21 , wherein the second impurity is an impurity which does not have a conductivity type.  
     
     
         24 . The method of  claim 21 , wherein the first impurity is an n-type impurity, and 
 wherein the second impurity is an impurity which increases a lattice constant of the gate electrode.    
     
     
         25 . The method of  claim 21 , wherein the first impurity is a p-type impurity, and 
 wherein the second impurity is an impurity which reduces a lattice constant of the gate electrode.    
     
     
         26 . The method of  claim 20 , further comprising the step f) of forming, on a side of the gate electrode, a dummy gate electrode containing a third impurity which changes an intrinsic lattice constant of a material forming the dummy gate electrode, 
 wherein in the step e), the impurity doped regions are formed so that each of the impurity doped regions is located between the dummy gate electrode and the gate electrode.    
     
     
         27 . A method for fabricating a semiconductor device, the method comprising the steps of: 
 a) forming, in a substrate including an active region formed therein, an isolation region so as surround the active region;    b) forming a gate insulation film and a gate electrode over the active region;    c) forming, at least in part of the substrate located over the active region and on a side of the gate electrode, a dummy gate electrode containing a first impurity which changes an intrinsic lattice constant of a material forming the dummy gate electrode; and    d) forming impurity doped regions each containing a second impurity having a conductivity type in parts of the active region located on both sides of the gate electrode, respectively, each of the parts being located between the gate electrode and the dummy gate electrode.    
     
     
         28 . The method of  claim 27 , wherein the step c) includes the steps of 
 c1) forming a gate material film over the substrate,    c2) patterning the gate material film to form the dummy gate electrode on a side of the gate electrode, and    c3) introducing the first impurity which changes a lattice constant of the gate material film at least into the dummy gate electrode,    wherein the step c2) is performed simultaneously with the step b).    
     
     
         29 . The method of  claim 28 , wherein the step c3), the first impurity is also introduced into part of the active region located between the gate electrode and the dummy gate electrode and in the vicinity of the dummy gate electrode to form a tensile impurity region, and 
 wherein in the step d), the impurity doped regions are formed in the parts of the active region including the tensile impurity region.    
     
     
         30 . The method of  claim 27 , wherein in the step c) includes the steps of 
 c4) forming a gate material film over the substrate,    c5) introducing the first impurity which changes a lattice constant of the gate material film in part of the gate material film, and    c6) patterning the gate material film to form the dummy gate electrode containing the first impurity,    wherein the step c6) is performed simultaneously with the step b) and the gate electrode formed in the step b) is formed of part of the gate material film in which the first impurity is not implanted in the step c5).    
     
     
         31 . The method of  claim 27 , wherein the second impurity is an n-type impurity, and 
 wherein the first impurity is an impurity which reduces a lattice constant of the gate material film.    
     
     
         32 . The method of  claim 27 , wherein the second impurity is a p-type impurity, and 
 wherein the first impurity is an impurity which increases a lattice constant of the gate material film.