Nitride-based transistors and fabrication methods with an etch stop layer

Abstract

A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

1 . A III-nitride based transistor comprising: 
 a substrate;    a first nitride-based layer on the substrate;    an etch stop layer on the first nitride-based layer;    a dielectric layer on the etch stop layer;    a gate recess that extends through the dielectric layer; and    a gate contact in the gate recess.    
   
   
       2 . The device of  claim 1 , wherein the gate recess extends through the etch stop layer to the first nitride-based layer and the gate contact in the gate recess electrically contacts the first nitride-based layer through the etch stop layer.  
   
   
       3 . The device of  claim 1 , wherein the etch stop layer comprises AlN, GaN, AlGaN, and/or SiO2.  
   
   
       4 . The device of  claim 1 , wherein the etch stop layer comprises sputtered AlN.  
   
   
       5 . The device of  claim 1  wherein the substrate comprises silicon carbide or sapphire.  
   
   
       6 . The device of  claim 1  wherein the transistor comprises a MESFET, JFET, MOSFET, MISHFET or an IGBT.  
   
   
       7 . The device of  claim 1 , wherein the dielectric layer comprises SiN, SiO2, and/or SiON.  
   
   
       8 . The device of  claim 1 , wherein the gate contact comprises a T gate structure.  
   
   
       9 . The device of  claim 1  further comprising: 
 a source/drain contact;    the gate contact further comprising a field plate extension that extends over at least a portion of the dielectric layer between the gate contact and the source/drain contact.    
   
   
       10 . The device of  claim 1 , further comprising an insulating layer between the first nitride-based layer and the gate contact.  
   
   
       11 . The device of  claim 10 , wherein the insulating layer comprises SiN, AlN, SiO 2 , and/or an ONO structure.  
   
   
       12 . The device according to  claim 1  that is configured to not fail catastrophically during high temperature, reverse bias stress testing.  
   
   
       13 . The device of  claim 1  that is configured to change less than about 1 dB in power output after high temperature, reverse bias stress testing.  
   
   
       14 . A device of  claim 1  that is configured to change less than about 0.3 db in power output after high temperature, reverse bias stress testing.  
   
   
       15 . The device of  claim 1  wherein the gate recess extends only partially through the etch stop layer and wherein the etch stop layer comprises a cap layer.  
   
   
       16 . The device of  claim 1  further comprising a cap layer between the etch stop layer and the first nitride-based layer.  
   
   
       17 . The device of  claim 16  wherein the gate recess extends through the dielectric layer and the etch stop layer to the cap layer.  
   
   
       18 . The device of  claim 16  wherein the cap layer comprises in-situ grown SiN.  
   
   
       19 . A III-nitride based high electron mobility transistor (HEMT) comprising: 
 a substrate;    a nitride-based first layer on the substrate wherein the first layer comprises GaN, AlGaN, InGaN, and/or AlInGaN;    a nitride-based second layer on the first layer wherein the second layer comprises GaN, AlN, AlGaN, AlInN, and/or AlInGaN and is different than the first layer;    a third layer on the second layer wherein the third layer comprises SiO2, GaN, AlGaN, and/or sputtered AlN, and is different than the second layer;    a fourth layer on the third layer wherein the fourth layer comprises SiN, SiO2, and/or SiON and is different than the third layer;    a gate recess that extends through the fourth layer; and    a gate contact in the gate recess.    
   
   
       20 . The device of  claim 19 , wherein the gate recess extends through the third layer to the second layer and the gate contact in the gate recess electrically contacts the second layer through the third layer.  
   
   
       21 . The device of  claim 19 , wherein the gate recess extends partially through the third layer and the gate contact in the gate recess does not electrically contact the second layer.  
   
   
       22 . The device of  claim 19  further comprising a fifth layer between the nitride-based second layer and the third layer, wherein the third layer comprises GaN, AlGaN, InGaN and/or SiN, and is different from the second and third layers.  
   
   
       23 . The device of  claim 22  wherein the gate recess extends through the third and fourth layers to the fifth layer.  
   
   
       24 . The device of  claim 23  wherein the SiN comprises in-situ grown SiN.  
   
   
       25 . A method of fabricating a III-nitride based transistor comprising: 
 forming a first nitride-based layer on a substrate;    forming an etch stop layer on the first nitride-based layer;    forming a dielectric layer on the etch stop layer wherein the dielectric layer is    different than the etch stop layer;    selectively etching the dielectric layer up to the etch stop layer to form a gate    recess that extends through the dielectric layer to the etch stop layer; and    forming a gate contact in the gate recess.    
   
   
       26 . The method of  claim 25 , further comprising 
 after selectively etching the dielectric layer to the etch stop layer, selectively etching the etch stop layer in the gate recess up to the first nitride-based layer.    
   
   
       27 . The method of  claim 25 , wherein selectively etching the dielectric layer comprises dry etching the dielectric layer with an etchant to which the etch stop layer is resistant.  
   
   
       28 . The method of  claim 27 , wherein dry etching the dielectric layer comprises etching with an etch species comprising SF 6 , SF 6 /O 2 , CF 4 , or CF 4 /O 2    
   
   
       29 . The method of  claim 27 , wherein after dry etching the dielectric layer, selectively etching the etch stop layer comprises wet etching the etch stop layer  
   
   
       30 . The method of  claim 29  wherein wet etching the etch stop layer comprises etching with a hydroxide-based developer, a heated hydroxide-based solution, BOE, or BHF.  
   
   
       31 . The method of  claim 29  wherein wet etching the etch stop layer comprises photo-enhanced electrochemical wet etching.  
   
   
       32 . The method of  claim 25  wherein the following is performed between forming the first nitride-based layer and forming the etch stop layer: 
 forming a cap layer on the first nitride-based layer, wherein the cap layer is different from the etch stop layer; and    wherein forming an etch stop layer comprises forming an etch stop layer on the cap layer, wherein the etch stop layer is different from the cap layer.    
   
   
       33 . The method of  claim 32  wherein forming the cap layer is performed by in-situ growth of SiN.