Encoding/decoding circuit

Abstract

An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding/decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

1 . An encoding/decoding circuit comprising: 
 an input portion;    an encoding/decoding operation portion;    an output portion; and    a data storage portion,    wherein said encoding/decoding operation portion includes    an encoding/decoding operation circuit for encoding or decoding data inputted through said input portion;    an avoiding path for causing said data inputted through said input portion to detour said encoding/decoding operation circuit; and    a selector for selectively outputting an output of said encoding/decoding operation circuit and an output of said avoiding path,    and wherein an output of said selector is given to said output portion and said data storage portion, and    said data storage portion gives data stored therein to said encoding/decoding operation portion.    
     
     
         2 . The encoding/decoding circuit according to  claim 1 , wherein 
 said data inputted through said input portion includes respective data of a plurality of channels,    said encoding/decoding circuit further comprising    a priority processing judgment portion for judging the priorities of said plurality of channels to be subject to encoding or decoding in said encoding/decoding operation circuit,    wherein said priority processing judgment portion judges said priorities by assigning predetermined states which define said priorities to said plurality of channels and moving each of said plurality of channels among said predetermined states on the basis of a processing request to each of said plurality of channels for encoding or decoding.    
     
     
         3 . An encoding/decoding circuit comprising: 
 an encoding/decoding operation portion; and    a key storage portion,    wherein said key storage portion includes a plurality of memory portions for one channel of input data which is to be subject to encoding or decoding in said encoding/decoding operation portion,    one of said plurality of memory portions stores a first key for said encoding or said decoding, and    said encoding/decoding operation portion decodes said input data into a second key for said encoding or said decoding by using said first key stored in said one of said plurality of memory portions and stores said second key into another one of said plurality of memory portions.    
     
     
         4 . The encoding/decoding circuit according to  claim 3 , wherein 
 if said encoding/decoding operation portion decodes said input data into a third key for said encoding or said decoding by using said second key stored in said another one of said plurality of memory portions, said encoding/decoding operation portion stores said third key into any of said plurality of memory portions other than said one memory portion.    
     
     
         5 . An encoding/decoding circuit comprising: 
 an encoding/decoding operation portion; and    a key storage portion,    wherein said key storage portion includes a first memory portion and a plurality of second memory portions corresponding to a plurality of channels of input data which is to be subject to encoding or decoding in said encoding/decoding operation portion, respectively,    said first memory portion stores a first key for said encoding or said decoding, which is common to said plurality of channels, and    said encoding/decoding operation portion decodes said input data into a second key for said encoding or said decoding by using said first key stored in said first memory portion and stores said second key into one of said plurality of second memory portions.    
     
     
         6 . The encoding/decoding circuit according to  claim 5 , wherein 
 if said encoding/decoding operation portion decodes said input data into a third key for said encoding or said decoding by using said second key stored in one of said plurality of second memory portions, said encoding/decoding operation portion stores said third key into one of said plurality of second memory portions other than said first memory portion.    
     
     
         7 . An encoding/decoding circuit comprising: 
 a key storage portion;    a decoding operation portion for decoding input data which is to be subject to decoding to obtain a second key for said decoding by using a given first key and stores said second key into said key storage portion; and    a key validity judgment circuit,    wherein said key validity judgment circuit activates a key valid signal indicating said second key is valid if said decoding operation portion obtains said second key through decoding by using said first key, and    said key validity judgment circuit inactivates said key valid signal if said second key is obtained through decoding by using a key other than said first key.    
     
     
         8 . The encoding/decoding circuit according to  claim 7 , wherein 
 said key valid signal is given to said decoding operation portion, and    said decoding operation portion stops said decoding or discards an operation result of said decoding if said key valid signal is inactivated.    
     
     
         9 . An encoding/decoding circuit comprising: 
 a key storage portion;    an encoding/decoding operation portion which uses a given encoding key, for generating a decoding key to decode input data which is encoded by said encoding key, and storing said decoding key into said key storage portion; and    a decoding key validity judgment circuit,    wherein said decoding key validity judgment circuit activates a decoding key valid signal indicating said decoding key is valid if said encoding/decoding operation portion generates said decoding key by using said encoding key, and    said decoding key validity judgment circuit inactivates said decoding key valid signal if said decoding key is generated by using a key other than said encoding key.    
     
     
         10 . The encoding/decoding circuit according to  claim 9 , wherein 
 said decoding key valid signal is given to said encoding/decoding operation portion, and    said encoding/decoding operation portion stops said decoding or discards an operation result of said decoding if said decoding key valid signal is inactivated.    
     
     
         11 . An encoding/decoding circuit comprising: 
 a key storage portion in which a first generation encoding key is stored;    an encoding/decoding operation portion; and    an encoding key/decoding key generation coincidence judgment circuit,    wherein said encoding/decoding operation portion uses said first generation encoding key to generate a second generation encoding key for encoding input data, and updates said first generation encoding key and stores said second generation encoding key into said key storage portion,    said encoding/decoding operation portion sequentially uses an n-th (n: natural number) generation encoding key to generate an (n+1)th generation encoding key for encoding said input data, and updates said n-th generation encoding key and stores said (n+1)th generation encoding key into said key storage portion,    said encoding/decoding operation portion uses said first generation encoding key to generate a first generation decoding key for decoding said input data which is encoded by said first generation encoding key and stores said first generation decoding key into said key storage portion,    said encoding/decoding operation portion sequentially uses encoding keys until the (n+1)th generation to generate decoding keys until the (n+1)th generation for decoding said input data, respectively, and updates an n-th generation decoding key and stores said (n+1)th generation decoding key into said key storage portion,    said encoding key/decoding key generation coincidence judgment circuit activates an encoding key/decoding key generation coincidence signal indicating said n-th generation decoding key is valid if said encoding/decoding operation portion generates said n-th generation decoding key by using said corresponding n-th generation encoding key, and    said encoding key/decoding key generation coincidence judgment circuit inactivates said encoding key/decoding key generation coincidence signal if said n-th generation decoding key is generated by using a key other than said corresponding n-th generation encoding key.    
     
     
         12 . The encoding/decoding circuit according to  claim 11 , wherein 
 said encoding key/decoding key generation coincidence signal is given to said encoding/decoding operation portion, and    said encoding/decoding operation portion stops said decoding or discards an operation result of said decoding if said encoding key/decoding key generation coincidence signal is inactivated.    
     
     
         13 . An encoding/decoding circuit comprising: 
 a key storage portion in which a first generation encoding key is stored;    an encoding/decoding operation portion; and    an encoding key/decoding key generation permission circuit,    wherein said encoding/decoding operation portion uses said first generation encoding key to generate a second generation encoding key for encoding input data, and updates said first generation encoding key and stores said second generation encoding key into said key storage portion,    said encoding/decoding operation portion sequentially uses an n-th (n: natural number) generation encoding key to generate an (n+1)th generation encoding key for encoding said input data, and updates said n-th generation encoding key and stores said (n+1)th generation encoding key into said key storage portion,    said encoding/decoding operation portion uses said first generation encoding key to generate a first generation decoding key for decoding said input data which is encoded by said first generation encoding key and stores said first generation decoding key into said key storage portion,    said encoding/decoding operation portion sequentially uses encoding keys until the (n+1)th generation to generate decoding keys until the (n+1)th generation for decoding said input data, and updates an n-th generation decoding key and stores said (n+1)th generation decoding key into said key storage portion,    said encoding key/decoding key generation permission circuit generates an encoding key/decoding key n-th generation permission signal indicating said decoding keys until the n-th generation are generated every time when said n-th generation decoding key is generated if said encoding/decoding operation portion generates said n-th generation decoding key to be valid by using said corresponding n-th generation encoding key.    
     
     
         14 . An encoding/decoding circuit comprising: 
 an encoding/decoding operation portion;    a key storage portion; and    a start key output circuit including a combination of a plurality of logic gate circuits, for generating a predetermined signal by using said combination and outputting said predetermined signal as a start key,    wherein said encoding/decoding operation portion encodes a given first key for encoding or decoding input data by using said start key and stores said first key into said key storage portion.    
     
     
         15 . The encoding/decoding circuit according to  claim 14 , further comprising 
 a validity evaluation key output circuit for outputting a validity evaluation key which is a predetermined signal; and    another key storage portion,    wherein said encoding/decoding operation portion decodes a given second key by using said validity evaluation key,    said encoding/decoding operation portion obtains a first hash value of said first key by using said decoded second key and stores said first hash value into said another key storage portion when said encoded first key is stored into said another key storage portion, and    said encoding/decoding operation portion obtains a second hash value of said first key read out from said another key storage portion by using said decoded second key and compares said first hash value with said second hash value when said encoding or said decoding is performed by using said first key.    
     
     
         16 . The encoding/decoding circuit according to  claim 14 , further comprising 
 a debugger verification key output circuit for outputting a debugger verification key which is a predetermined signal,    wherein said encoding/decoding operation portion encodes or decodes predetermined verification data by using said debugger verification key, and    said encoding/decoding operation portion stops encoding or decoding of said input data unless a password coincident with said verification data is inputted if it detects that a debugger is used.    
     
     
         17 . The encoding/decoding circuit according to  claim 16 , further comprising 
 a validity evaluation key output circuit for outputting a validity evaluation key which is a predetermined signal,    wherein said encoding/decoding operation portion decodes a given second key by using said validity evaluation key,    said encoding/decoding operation portion obtains a first hash value of said first key by using said decoded second key and stores said first hash value into said another key storage portion when said encoded first key is stored into said key storage portion,    said encoding/decoding operation portion obtains a second hash value of said first key read out from said key storage portion by using said decoded second key and compares said first hash value with said second hash value when said encoding or said decoding is performed by using said first key, and    said encoding/decoding operation portion stops encoding or decoding of said input data if said first hash value is different from said second hash value, even if a password coincident with said encoded or decoded verification data is inputted.    
     
     
         18 . The encoding/decoding circuit according to  claim 15 , wherein 
 said input data can be transmitted not through said encoding/decoding operation portion, and    said transmission of said input data is stopped if said first hash value is different from said second hash value.    
     
     
         19 . The encoding/decoding circuit according to  claim 16 , wherein 
 said input data can be transmitted not through said encoding/decoding operation portion, and    said transmission of said input data is stopped if it is detected that a debugger is used and said password is not inputted.