Semiconductor device having an integrated, self-regulated PWM current and power limiter and method

Abstract

A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.

1 . A method, comprising: 
 receiving an activation signal at a semiconductor device;    generating an output power signal at the semiconductor device in response to receiving the activation signal, the output power signal having a duty cycle;    providing the output power signal to a load, the output power signal providing power to the load, an amount of power provided to the load based on the duty cycle of the output power signal; and    adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.    
   
   
       2 . The method of  claim 1 , wherein receiving the activation signal comprises receiving the activation signal from a controller that is external to the semiconductor device.  
   
   
       3 . The method of  claim 1 , wherein generating the output power signal comprises driving a transistor coupled between a power supply and the load into conducting and non-conducting states to produce the output power signal.  
   
   
       4 . The method of  claim 1 , wherein adjusting the duty cycle of the output power signal comprises: 
 measuring at least one of a power level and a current level of the output power signal; and    adjusting the duty cycle of the output power signal based on at least one of the measured power level and the measured current level.    
   
   
       5 . The method of  claim 1 , further comprising: 
 detecting a problem in the semiconductor device; and    placing the semiconductor device in a self-limiting mode in which at least one of a reduced amount of current and a reduced amount of power is provided to the load.    
   
   
       6 . The method of  claim 5 , wherein detecting the problem in the semiconductor device comprises: 
 measuring one or more temperatures within the semiconductor device; and    comparing at least one of (i) the one or more measured temperatures and (ii) one or more calculated temperature rise times and gradients to one or more thresholds.    
   
   
       7 . The method of  claim 5 , further comprising providing another output signal that is proportional to the output power signal.  
   
   
       8 . The method of  claim 1 , wherein the semiconductor device performs the receiving, generating, providing, and adjusting steps in a stand-alone mode without any external controller.  
   
   
       9 . The method of  claim 1 , wherein the load comprises one or more of: a motor, a solenoid, and a lamp in a vehicle.  
   
   
       10 . A semiconductor device, comprising: 
 an output power signal generator capable of generating an output power signal, the output power signal having a duty cycle and providing power to a load, an amount of power provided to the load based on the duty cycle of the output power signal;    a controller capable of causing the output power signal generator to generate the output power signal in response to receiving an activation signal; and    at least one of a current limiter and a power limiter capable of adjusting the duty cycle of the output power signal.    
   
   
       11 . The semiconductor device of  claim 10 , wherein at least one of the current limiter and the power limiter is capable of adjusting the duty cycle of the output power signal independent of the activation signal.  
   
   
       12 . The semiconductor device of  claim 10 , wherein the output power signal generator comprises a transistor coupled between a power supply and the load; and 
 further comprising a driver capable of driving the transistor into conducting and non-conducting states to produce the output power signal, the driver capable of being controlled by the controller, the current limiter, and the power limiter.    
   
   
       13 . The semiconductor device of  claim 10 , wherein at least one of the current limiter and the power limiter is capable of adjusting the duty cycle of the output power signal by: 
 measuring at least one of a power level and a current level of the output power signal; and    adjusting the duty cycle of the output power signal based on at least one of the measured power level and the measured current level.    
   
   
       14 . The semiconductor device of  claim 10 , further comprising: 
 a fault storage buffer capable of storing a fault condition identifying a problem in the semiconductor device; and    a tri-state buffer capable of providing another output signal that is proportional to the output power signal.    
   
   
       15 . The semiconductor device of  claim 10 , wherein the semiconductor device operates in a stand-alone mode without any external controller.  
   
   
       16 . A system, comprising: 
 a power supply capable of providing a supply voltage; and    a semiconductor device capable of: 
 generating an output power signal using the supply voltage in response to an activation signal, the output power signal having a duty cycle;  
 providing the output power signal to a load, an amount of power provided to the load based on the duty cycle of the output power signal; and  
 adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device.  
   
   
   
       17 . The system of  claim 16 , wherein the semiconductor device further comprises: 
 a transistor coupled between the power supply and the load;    a driver capable of driving the transistor into conducting and non-conducting states to produce the output power signal; and    a controller capable of controlling the driver.    
   
   
       18 . The system of  claim 16 , wherein at least one of the current limiter and the power limiter is capable of adjusting the duty cycle of the output power signal by: 
 measuring at least one of a power level and a current level of the output power signal; and    adjusting the duty cycle of the output power signal based on at least one of the measured power level and the measured current level.    
   
   
       19 . The system of  claim 16 , wherein the semiconductor device further comprises: 
 a controller capable of placing the semiconductor device in a self-limiting mode in which at least one of a reduced amount of current and a reduced amount of power is provided to the load when a problem in the semiconductor device is detected;    a fault storage buffer capable of storing a fault condition identifying the problem in the semiconductor device; and    a tri-state buffer capable of providing another output signal that is proportional to the output power signal.    
   
   
       20 . The system of  claim 16 , further comprising an external controller coupled to the semiconductor device by a single connection, the external controller capable of providing the activation signal to the semiconductor device.