US2007013076A1PendingUtilityA1

Semiconductor device and method of manufacturing thereof

Assignee: AKIYAMA KAZUTAKAPriority: Jul 15, 2005Filed: May 18, 2006Published: Jan 18, 2007
Est. expiryJul 15, 2025(expired)· nominal 20-yr term from priority
H10P 95/08H10P 50/287H10P 50/283H10W 20/0888H10W 20/0886H10W 20/0698H10W 20/098H10W 20/085H10W 20/069H10W 20/089
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Claims

Abstract

A first conductive layer and a second conductive layer are formed on an upper surface of a semiconductor substrate. The second conductive layer formed at a higher location than the first conductive layer. An insulating film is formed over the semiconductor substrate to cover the first conductive layer and the second conductive layer. An interlayer insulator has a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on the first layered film. The interlayer insulator is formed covering the first conductive layer and the second conductive layer.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device, comprising: 
 a semiconductor substrate having an upper surface with a first conductive layer and a second conductive layer formed thereon, said second conductive layer formed at a higher location than said first conductive layer;    an insulating film formed over said semiconductor substrate to cover said first conductive layer and said second conductive layer; and    an interlayer insulator having a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material and formed on said first layered film, said interlayer insulator formed on said insulating film to cover said first conductive layer and said second conductive layer.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein said first layered film has a height at an upper surface thereof almost coincident with a height of said insulating film.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein said first layered film is planarized through a CMP process using a slurry of an organic material with a stopper film of said insulating film.  
   
   
       4 . The semiconductor device according to  claim 3 , wherein said slurry comprises a resin.  
   
   
       5 . The semiconductor device according to  claim 3 , wherein said insulating film is a silicon nitride film.  
   
   
       6 . The semiconductor device according to  claim 1 , wherein said first layered film is an impurity-diffused region formed on said upper surface of said semiconductor substrate, and 
 wherein said second layered film is a gate electrode of a MOS transistor formed on said semiconductor substrate with an insulating film interposed therebetween.    
   
   
       7 . The semiconductor device according to  claim 1 , wherein said first layered film comprises a polyallylene-based organic film and said second layered film comprises a tetraethoxysilane film.  
   
   
       8 . A method of manufacturing a semiconductor device, comprising: 
 forming a first conductive layer and a second conductive layer located higher than said first conductive layer on an upper surface of a semiconductor substrate;    forming an insulating film over said semiconductor substrate including said first conductive layer and said second conductive layer;    forming an interlayer insulator having a structure of at least two layers including a first layered film composed of an organic insulating material and a second layered film composed of an inorganic insulating material formed on said first layered film, said interlayer insulator formed via said insulating film to cover said first conductive layer and said second conductive layer; and    etching said second layered film under a first etching condition and etching said first layered film under a different etching condition from said first etching condition to form contact holes on said second conductive layer and said first conductive layer.    
   
   
       9 . The method according to  claim 8 , further comprising planarizing said first layered film through a CMP process with a stopper film of said insulating film after formation of said first layered film covering said second layered film.  
   
   
       10 . The method according to  claim 9 , wherein said CMP process uses a slurry of an organic material.  
   
   
       11 . The method according to  claim 10 , wherein said slurry comprises a resin.  
   
   
       12 . The method according to  claim 8 , wherein said first etching condition includes a selective ratio of said first layered film to said second layered film larger than a certain value, and wherein said second etching condition includes a selective ratio of said first layered film to said insulating film larger than a certain value.  
   
   
       13 . The method according to  claim 8 , wherein said insulating film is a silicon nitride film.  
   
   
       14 . The method according to  claim 8 , wherein said first layered film is formed through spin coating and then thermally cured.

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