Memory cell with selective deposition of refractory metals

Abstract

Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then, an immersion plating process is used to replace the atoms of the sacrificial layer with atoms of a desired metal, such as platinum, thereby creating a metal cap isolated within the via. The advantages of planarization to isolate material within recessed via are thus obtained without having to planarize or otherwise etch the desired metal. The cap layer can be further reacted to form a barrier compound prior to forming a capacitor over the plug. Advantageously, the plug structure resists oxidation during fabrication of overlying capacitors that incorporate high dielectric constant materials.

1 - 13 . (canceled)  
   
   
       14 . A memory cell in an integrated circuit, comprising: 
 a semiconductor substrate;    an insulating layer over the semiconductor substrate;    a via extending through the insulating layer; and    an electrically conductive conduit within the via, the conduit comprising: 
 a first portion in electrical contact with the substrate; and  
 a second portion over the first portion and electrically coupled to the first portion, the second portion confined to the via and having a surface facing away from the substrate, the second portion comprising platinum or an alloy of platinum and one or more other noble metals.  
   
   
   
       15 . The memory cell of  claim 14 , wherein the conduit is in electrical contact with a transistor of the substrate.  
   
   
       16 . The memory cell of  claim 14 , wherein the insulating layer comprises borophosphosilicate glass (BPSG).  
   
   
       17 . The memory cell of  claim 14 , wherein the insulating layer has a thickness between about 0.5 micron to 2.0 microns.  
   
   
       18 . The memory cell of  claim 14 , wherein the via has a width between about 0.10 micron and 0.5 micron.  
   
   
       19 . The memory cell of  claim 14 , wherein the via has a width between about 0.15 micron and 0.25 micron.  
   
   
       20 . The memory cell of  claim 14 , wherein the via has a substantially circular cross-section.  
   
   
       21 . The memory cell of  claim 14 , wherein the first portion comprises polysilicon.  
   
   
       22 . The memory cell of  claim 14 , wherein the first portion comprises tungsten or a metal silicide.  
   
   
       23 . The memory cell of  claim 14 , wherein the first portion is recessed from a top surface of the insulating layer by a distance between about 500 Angstroms and 10,000 Angstroms.  
   
   
       24 . The memory cell of  claim 14 , wherein the first portion is recessed from a top surface of the insulating layer by a distance between about 1,000 Angstroms and 5,000 Angstroms.  
   
   
       25 . The memory cell of  claim 14 , wherein the first portion is recessed from a top surface of the insulating layer by a distance between about 1,500 Angstroms and 2,000 Angstroms.  
   
   
       26 . The memory cell of  claim 14 , wherein the first portion comprises a titanium silicide layer and a titanium nitride layer.  
   
   
       27 . The memory cell of  claim 14 , wherein the memory cell further comprises a capacitor over and electrically coupled to the second portion, the capacitor comprising a dielectric material with a dielectric constant greater than about  10 .  
   
   
       28 . The memory cell of  claim 27 , wherein the dielectric material comprises Ta 2 O 5  or BST.  
   
   
       29 . A system including an integrated circuit comprising: 
 a semiconductor substrate;    an insulating layer over the semiconductor substrate;    a via extending through the insulating layer; and    an electrically conductive conduit within the via, the conduit comprising: 
 a first portion in electrical contact with the substrate; and  
 a second portion over the first portion and electrically coupled to the first portion, the second portion confined to the via and having a surface facing away from the substrate, the second portion comprising platinum or an alloy of platinum and one or more other noble metals.  
   
   
   
       30 . The system of  claim 29 , wherein the integrated circuit is a dynamic random access memory element.  
   
   
       31 . A method of filling a recess, the method comprising: 
 providing an electrically insulating layer;    forming a recess within the electrically insulating layer;    partially filling the recess with one or more electrically conductive materials;    depositing a first material into the partially filled recess and over the electrically insulating layer, the first material in electrical contact with the one or more electrically conductive materials;    removing a portion of the first material from over the electrically insulating layer; and    replacing atoms of the first material within the recess with atoms of a second material.    
   
   
       32 . The method of  claim 31 , wherein removing a portion of the first material from over the electrically insulating layer comprises planarizing.  
   
   
       33 . The method of  claim 32 , wherein planarizing comprises a chemical mechanical polish.  
   
   
       34 . The method of  claim 31 , wherein the first material is readily oxidized and removed by chemical mechanical planarization.  
   
   
       35 . The method of  claim 31 , wherein the first material is selected from the group consisting of: copper, aluminum, tungsten, and titanium.  
   
   
       36 . The method of  claim 31 , wherein the second material is resistant to oxidation.  
   
   
       37 . The method of  claim 31 , wherein the second material is selected from the group consisting of: gold, platinum, palladium, silver, iridium, ruthenium, rhodium, and osmium.  
   
   
       38 . The method of  claim 31 , wherein replacing comprises conducting an immersion plating process.  
   
   
       39 . The method of  claim 31 , wherein partially filling the recess comprises blanket depositing the one or more electrically conductive materials within the recess and removing a portion of the one or more electrically conductive materials from within the recess.  
   
   
       40 . The method of  claim 39 , wherein recessing comprises a reactive ion etch.  
   
   
       41 . The method of  claim 39 , wherein recessing comprises a wet chemical etch.  
   
   
       42 . The method of  claim 31 , further comprising depositing iridium, rhodium, or ruthenium over the second material and alloying the deposited iridium, rhodium, or ruthenium with the second material.