Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same

Abstract

A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure. According to one embodiment of the present invention, a central patterning stop region and a pair of lateral patterning stop regions are provided such that the container region defines a container cross section having an upper container portion and a lower container portion, wherein the lower container portion is positioned between the lateral stop regions, and wherein the upper container portion is wider than the lower container portion.

1 . A memory device comprising: 
 a storage container structure comprising: 
 a substrate including a semiconductor structure;  
 a single layer of insulating material disposed over and in contact with said substrate, said insulating material of sufficient depth to include a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;  
 a charge storage lamina formed over an interior surface of said container region, said charge storage lamina comprising a first conductive film with at least a portion thereof in contact with said patterning stop region, a second conductive film defining a first surface thereon, and an insulating film disposed intermediate said first and second conductive films;  
 a contact region defined by said charge storage lamina, wherein said contact region defines a contact region cross section having contact region side walls and a contact region bottom wall, and wherein said contact region side walls and said contact region bottom wall are defined by said first surface of said second conductive film; and  
 an electrical contact in contact with said first surface of said second conductive film such that said electrical contact and said second conductive film occupy collectively at least a portion of said container region; and  
   a bit line terminal coupled to said charge storage lamina through a switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command.    
   
   
       2 . A device comprising: 
 a storage container structure including: 
 a substrate including a semiconductor structure;  
 a single layer of insulating material disposed over and in contact with said substrate, said insulating overlayer including a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;  
 a charge storage lamina formed over an interior surface of said container region, said charge storage lamina comprising a first conductive film with at least a portion thereof in contact with said patterning stop region, a second conductive film defining a first surface thereon, and an insulating film disposed intermediate said first and second conductive films such that a shape defined by said insulating and first and second conductive films define a contact region with a cross section having side walls and a bottom wall that are formed by said first surface of said second conductive film; and  
 an electrical contact disposed in said contact region, wherein respective portions of said electrical contact and said second conductive film occupy collectively at least a portion of said container region; and  
   a bit line terminal coupled to said charge storage lamina through a switching structure, wherein a charge transfer status of said switching structure changes in response to a memory access command.    
   
   
       3 . A memory device comprising: 
 a storage container structure including: 
 a substrate including a semiconductor structure;  
 a single layer of insulating material disposed over and in contact with said substrate, said insulating material of sufficient depth to include a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a transistor switching structure comprising a gate, a source and a drain, wherein at least one of said source and drain comprises a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region;  
 a capacitor formed over an interior surface of said container region, said capacitor comprising a first electrode in contact with said patterning stop region, an insulating layer disposed on top of said first electrode, and a second electrode disposed on top of said insulating layer, said capacitor configured such that a surface of said second electrode defines a contact region therein; and  
 an electrical contact disposed in said contact region, wherein respective portions of said electrical contact and said second electrode occupy collectively at least a portion of said container region; and  
   a bit line terminal coupled to said capacitor through said transistor switching structure.    
   
   
       4 . The memory device of  claim 1 , wherein said substrate comprises a single layer doped substrate.  
   
   
       5 . The memory device of  claim 4 , wherein said patterning stop region is in contact with said substrate.  
   
   
       6 . The memory device of  claim 5 , wherein said insulating film disposed intermediate said first and second conductive films comprises a dielectric layer.  
   
   
       7 . The device of  claim 2 , wherein said substrate comprises a single layer doped substrate.  
   
   
       8 . The device of  claim 7 , wherein said patterning stop region is in contact with said substrate.  
   
   
       9 . The device of  claim 8 , wherein said insulating film disposed intermediate said first and second conductive films comprises a dielectric layer.  
   
   
       10 . The device of  claim 9 , further comprising a microprocessor in communication with a plurality of said charge storage structures via respective ones of a plurality of said bit line terminals.  
   
   
       11 . The device of  claim 10 , further comprising a read-only-memory device, a mass memory device and at least one input/output device, all in signal communication with said microprocessor.  
   
   
       12 . The device of  claim 11 , wherein said at least one input/output device comprises a data input device and an output viewing device.  
   
   
       13 . (canceled)  
   
   
       14 . (canceled)  
   
   
       15 . The memory device of  claim 16 , wherein said insulating layer comprises a dielectric layer.  
   
   
       16 . A memory device comprising: 
 a storage container structure including: 
 a single layer doped substrate including a semiconductor structure;  
 a single layer of insulating material disposed over and in contact with said substrate, said insulating material of sufficient depth to include a container region disposed therein, said container region defining a container cross section having container side walls, a container bottom wall, and a container interior bounded in part by said container side walls and said container bottom wall;  
 a transistor switching structure comprising a gate, a source and a drain, wherein at least one of said source and drain comprises a patterning stop region disposed over said substrate such that all of said container bottom wall is defined by an upper surface of said patterning stop region, wherein a lower surface of said patterning stop region is in contact with said substrate, and lateral side surfaces of said patterning stop region are substantially surrounded by said single layer of insulating material disposed over and in contact with said substrate;  
 a capacitor formed over an interior surface of said container region, said capacitor comprising a first electrode in contact with said patterning stop region, an insulating layer disposed on top of said first electrode, and a second electrode disposed on top of said insulating layer, said capacitor configured such that a surface of said second electrode defines a contact region therein; and  
 an electrical contact disposed in said contact region, wherein respective portions of said electrical contact and said second electrode occupy collectively at least a portion of said container region; and  
   a bit line terminal coupled to said capacitor through said transistor switching structure.