Signal, storage medium, method and device for encoding, method and device for decoding

Abstract

The invention relates to a signal comprising a runlength limited (RLL) encoded binary d,k channel bitstream 3 , wherein parameter d defines a minimum number and parameter k defines a maximum number of zeroes between any two ones of said bitstream 3 or vice versa, comprising a number of sections of respectively N successive RLL channel bits, called RLL rows 8 - 13, 45 , each RLL row 8 - 13, 45 representing a parity-check code-word, called row parity-check code-word, in which a so-called row-based parity-check constraint for said RLL row 8 - 13, 45 has been realized, characterized in that K sections of respectively N successive channel bits, called column parity-check rows 21, 22, 43, 44, 46 , are located at predetermined positions of a group of M RLL rows 8 - 13, 45 , K, N and M being integer values, said column parity-check rows 21, 22, 43, 44, 46 comprising a plurality of column parity-check enabling channel words 30, 42, 48 , wherein each of said column parity-check check enabling channel words 30, 42, 48 realizes a so-called column-based parity-check constraint for all so-called corresponding segments 24 - 29 of at least said M RLL rows 8 - 13, 45 of said group that correspond to a specific column parity-check enabling channel word 30, 42, 48 ), hereby constituting a column parity-check codeword. Furthermore, the invention relates to a storage medium comprising such a signal as well as a method and a device for encoding a stream of user data bits into such a signal as well as a method and a device for decoding such a signal.

1 - 26 . (canceled)  
     
     
         27 . A signal comprising a runlength limited (RLL) encoded binary d,k channel bitstream, wherein parameter d defines a minimum number and parameter k defines a maximum number of zeroes between any two ones of said bitstream or vice versa, comprising: 
 a number of sections of respectively N successive RLL channel bits, called RLL rows, each RLL row representing a parity-check code-word, called row parity-check code-word, in which a so-called row-based parity-check constraint for said RLL row has been realized;    K sections of respectively N successive channel bits, called column parity-check rows, are located at predetermined positions of a group of M RLL rows, K, N and M being integer values, said column parity-check rows comprising a plurality of column parity-check enabling channel words,    wherein each of said column parity-check enabling channel words realizes a so-called column-based parity-check constraint for all so-called corresponding segments of at least said M RLL rows of said group that correspond to a specific column parity-check enabling channel word, hereby constituting a column parity-check codeword and    wherein w j  is a unique index associated with each word W j  which defines one of a number of possible d,k constrained sequences of said segment width (N 1 , N 2 ), wherein such a word W j  is comprised in each corresponding segment, and              w   j     =       ∑     i   =   0         N     1   ,   2       -   1       ⁢       b   i   j     ·       N   d     ⁡     (   i   )                   wherein b i   j  denotes bit number i of word W j  in row j and wherein N d (i) is the number of possible d,k constrained sequences of length i.    
     
     
         28 . (canceled)  
     
     
         29 . A storage medium storing a signal according to  claim 27 .  
     
     
         30 . A storage medium according to  claim 29 , characterized in that said storage medium is a recorded optical, magnetic, or magneto-optical disc or recoded magnetic tape.  
     
     
         31 - 34 . (canceled)  
     
     
         35 . A method for decoding a signal according to  claim 27 , the method comprising the steps of: 
 checking for each RLL row a so-called row-based parity-check constraint,    checking for each column parity-check segment of said column parity-check rows a so-called column-based parity-check constraint along all corresponding segments of at least said M RLL rows that correspond to said column parity-check enabling channel word, and    determining an erroneous channel word based on said checking steps.    
     
     
         36 . A method according to  claim 35 , wherein said determining step includes locating an erroneous segment at a crossing point of 
 a) an erroneous RLL row that violates said row-based parity-check constraint for said RLL row and    b) an erroneous column comprising all corresponding segments that correspond to a specific column parity-check enabling channel word, wherein said column violates said column-based parity-check constraint.    
     
     
         37 . A method according to  claim 36 , wherein an located erroneous segment is corrected if a single erroneous segment occurs.  
     
     
         38 . A method according to  claim 35 , wherein said determining step is further based on channel side-information if more than a single erroneous segment occurs.  
     
     
         39 . A method according to  claim 38 , wherein said channel side-information is phase-error information of bit transitions in the channel words of the segments at said crossing points.  
     
     
         40 . A method according to  claim 39 , wherein a phase-error with the largest absolute value is determined and the corresponding one-bit of the d,k channel bitstream is shifted by one bit position.  
     
     
         41 . A method according to  claim 35 , wherein said signal comprises said column parity-check enabling channel words at every second channel bit position only, and wherein said determining step includes, upon detecting a first erroneous column, the step of deciding whether another erroneous column is positioned to the left or to the right of said first erroneous column.  
     
     
         42 . A method according to  claim 41 , wherein said decision step is based on channel-side information.  
     
     
         43 . A method according to  claim 35 , wherein said signal comprises segments of more than one successive channel bits of alternating segment width N 1  or N 2 , and wherein a single-bit transition-shift error is determined internal of such a segment, namely 
 a) a transition-shift error is determined from bit position i to the right to bit position i+1, if the detected column-based parity-check constraint is detected as        V   as-detected   =N   d ( i+ 1)− N   d ( i )    and    b) a transition-shift error is determined from bit position i to the left to bit position i−1, if the detected column-based parity-check constraint is detected as        V   as-detected   =N   d ( i− 1)− N   d ( i )    wherein N d (i−1), N d (i) N d (i+1) are the numbers of possible d,k constrained sequences of length i−1, i, i+1, respectively.    
     
     
         44 . A method according to  claim 35 , wherein said signal comprises segments of more than one successive channel bits of alternating segment width N 1  or N 2 , and wherein a single-bit transition-shift error is determined crossing the left boundary of such a segment, namely 
 a) a transition-shift error is determined from the last bit position of the previous segment to the first bit position of the present segment, if the detected column-based parity-check constraint is detected for the present column as        V   as-detected, present   =+N   d (0)    and if the detected column-based parity-check constraint is detected for the previous column as        V   as-detected, previous   =−N   d ( N   1,2 −1)    or    b) a transition-shift error is determined from the first bit position of the present segment to the last bit position of the previous segment, if the detected column-based parity-check constraint is detected for the present column as        V   as-detected, present   −N   d (0)    and if the detected column-based parity-check constraint is detected for the previous column as        V   as-detected, previous   +N   d ( N   1,2 −1)    wherein N d (0)=1 and N d (N 1,2 −1) is the number of possible d,k constrained sequences of length N 1,2 −1.    
     
     
         45 . A method according to  claim 35 , wherein said signal comprises segments of more than one successive channel bits of alternating segment width N 1  or N 2 , and wherein a single-bit transition-shift error is determined crossing the right boundary of such a segment, namely 
 a) a transition-shift error is determined from the last bit position of the present segment to the first bit position of the subsequent segment, if the detected column-based parity-check constraint is detected for the present column as        V   as-detected, present   =−N   d ( N   1,2 −1)    and if the detected column-based parity-check constraint is detected for the subsequent column as        V   as-detected, subsequent   =+N   d (0)    or    b) a transition-shift error is determined from the first bit position of the subsequent segment to the last bit position of the present segment, if the detected column-based parity-check constraint is detected for the present column as        V   as-detected, present   =+N   d (N 1,2 −1)    and if the detected column-based parity-check constraint is detected for the subsequent column as        V   as-detected, subsequent   =−N   d (0)    wherein N d (0)=1 and N d (N 1,2 −1) is the number of possible d,k constrained sequences of length N 1,2 −1.    
     
     
         46 . A method according to  claim 43 , wherein a segment with a determined single-bit transition-shift error is corrected by being replaced by a segment having said unique index  
       
         
        
         w 
         j 
         =w′ 
         j 
         −V 
         as-detected  
        
       
       wherein w′ j  is an as-detected index of said segment to be replaced, wherein  
       
         
           
             
               
                 w 
                 j 
                 ′ 
               
               = 
               
                 
                   ∑ 
                   
                     i 
                     = 
                     0 
                   
                   
                     
                       N 
                       
                         1 
                         , 
                         2 
                       
                     
                     - 
                     1 
                   
                 
                 ⁢ 
                 
                   
                     b 
                     i 
                     
                       ′ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       j 
                     
                   
                   · 
                   
                     
                       N 
                       d 
                     
                     ⁡ 
                     
                       ( 
                       i 
                       ) 
                     
                   
                 
               
             
           
         
       
       wherein b′ i   j  denotes as-detected bit-value for the bit with number i of said segment in row j and wherein N d (i) is the number of possible d,k constrained sequences of length i.  
     
     
         47 . A device for decoding a signal according to  claim 27  comprising: 
 parity-check means for checking for each RLL row a row-based parity-check constraint, and for checking for each column parity-check enabling channel word of said column parity-check rows a so-called column-based parity-check constraint along all corresponding segments of at least said M RLL rows that correspond to said column parity-check enabling channel word, and    determining means for determining an erroneous channel word based on the result of said parity-checking.    
     
     
         48 . A device according to  claim 47 , wherein said device comprising means for performing a method according to  claim 35.