Erase verify for non-volatile memory

Abstract

A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.

1 . A method for erasing a flash memory device, the method comprising: 
 pre-programming flash memory cells;    applying erase pulses to the flash memory cells and performing an erase verification of the flash memory cells; and    healing over-erased ones of the flash memory cells without performing a separate leakage detection operation.    
   
   
       2 . The method of  claim 1  wherein over-erased flash memory cell addresses are latched during the erase verification of the flash memory cells.  
   
   
       3 . The method of  claim 1  wherein healing over-erased flash memory cells is embedded within performing the erase verification of the flash memory cells.  
   
   
       4 . The method of  claim 1  wherein the flash memory device comprises a bit line coupled to each column of flash memory cells.  
   
   
       5 . The method of  claim 4  wherein over-erased ones of the flash memory cells are cells having a bit line current of 100 μA or greater, erase verified flash memory cells are cells having a bit line current of at least 70 μA and less than 100 μA, and under erased flash memory cells are cells having a bit line current of 40 μA or less.  
   
   
       6 . The method of  claim 4  wherein erase status information and cell addresses of the over-erased ones of the flash memory cells are stored prior to healing the over-erased flash memory cells.  
   
   
       7 . The method of  claim 4  wherein status information and cell addresses of the over-erased ones of the flash memory cells are used during the healing of the over-erased flash memory cells.  
   
   
       8 . The method of  claim 4  wherein a voltage applied to each flash memory cell causes a bit line current indicating an erased state of the flash memory cell.  
   
   
       9 . A method for erasing a flash memory device, the method comprising: 
 pre-programming flash memory cells;    applying erase pulses to the flash memory cells; and performing an erase verification of the flash memory cells that includes healing of over-erased ones of the flash memory cells.    
   
   
       10 . The method of  claim 9  wherein the erase verification comprises determining a bit line current of a bit line coupled to a column of flash memory cells of the flash memory device.  
   
   
       11 . The method of  claim 10  wherein the bit line current is determined by a comparator circuit coupled to the bit line.  
   
   
       12 . The method of  claim 11  wherein the comparator circuit compares the bit line current to a reference current.  
   
   
       13 . The method of  claim 10  and further including: 
 converting the bit line current to a bit line voltage; and    comparing the bit line voltage to a reference voltage.    
   
   
       14 . The method of  claim 10  and further including: 
 converting the bit line current to a bit line voltage; and    comparing the bit line voltage to a plurality of reference voltages.    
   
   
       15 . A method for erasing a non-volatile memory, the method comprising: 
 pre-programming a plurality of non-volatile memory cells;    performing an erase operation on the plurality of non-volatile memory cells including an erase verification during which an address and erase status of each non-volatile memory cell is determined;    storing the address and erase status of the over-erased non-volatile memory cells; and if the erase verification determines that any of the plurality of non-volatile memory cells is over-erased, soft programming the over-erased non-volatile memory cells, without performing a separate leakage detection operation, in response to the stored address and erase status.    
   
   
       16 . The method of  claim 15  wherein the leakage detection operation is performed substantially simultaneously with the erase verification.  
   
   
       17 . The method of  claim 15  and further including if the erase verification determines that at least one of the plurality of non-volatile cells is under-erased, performing an additional erase operation on the at least one cell.  
   
   
       18 . A method for erasing a non-volatile memory comprising a plurality of bit lines coupled to columns of non-volatile memory cells, each cell having an address and an erase status, the method comprising: pre-programming a plurality of non-volatile memory cells; 
 performing an erase operation on the plurality of non-volatile memory cells including an erase verification during which an address and erase status of each non-volatile memory cell is determined; and if the erase verification determines that any of the plurality of non-volatile memory cells is over-erased, soft programming the over-erased non-volatile memory cells, without performing a separate leakage detection operation, in response to the address and erase status.    
   
   
       19 . The method of  claim 18  wherein the erase verification is performed by a verify circuit that is coupled to the bit lines wherein the verify circuit comprises first and second comparators, the first comparator generating an upper reference current and the second comparator generating a lower reference current.  
   
   
       20 . The method of  claim 19  wherein the erase verification comprises: 
 comparing a first bit line current with the upper and lower reference currents;    if the first bit line current of a first memory cell is less than the lower reference current, storing the address and the under-erased status indication; and    if the first bit line current of the first memory cell is greater than the upper reference current, storing the address and the over-erased status indication.