US2007007615A1PendingUtilityA1

Devices containing multiple undercut profiles

Assignee: HUANG KARENPriority: Feb 16, 1999Filed: May 17, 2006Published: Jan 11, 2007
Est. expiryFeb 16, 2019(expired)· nominal 20-yr term from priority
H01J 29/481H01J 9/025H01J 9/24H01J 31/127
55
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Claims

Abstract

Devices including multiple undercut profiles in a single material are disclosed. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device structure comprising: 
 a first dielectric layer overlying a substrate, the first dielectric layer including a first opening having a first perimeter;    a conductive layer overlying the first dielectric layer, the conductive layer including a second opening having a second perimeter smaller than the first perimeter; and    a second dielectric layer overlying the conductive layer, the second dielectric layer having a third opening having a third perimeter larger than the second perimeter and smaller than the first perimeter.    
     
     
         2 . The semiconductor device structure of  claim 1 , wherein the first dielectric layer and the second dielectric layer comprise silicon dioxide.  
     
     
         3 . The semiconductor device structure of  claim 1 , wherein the conductive layer is selected from doped polycrystalline silicon and a conductive metal.  
     
     
         4 . The semiconductor device structure of  claim 3 , wherein the conductive layer is chromium.  
     
     
         5 . The semiconductor device structure of  claim 1 , further comprising a polymer film plug in contact with the second dielectric layer and extending to an edge of the second opening.  
     
     
         6 . An intermediate semiconductor device structure comprising: 
 a substrate having a conical cathode emitter tip thereon;    a first insulating layer over the cathode emitter tip;    a conductive layer overlying the first insulating layer, the conductive layer including a first opening having a first diameter which exposes at least the first insulating layer;    a second insulating layer and a metal layer overlying the conductive layer, the second insulating layer and metal layer including a second opening defined by substantially aligned sidewalls of the second insulating layer and the metal layer, the second opening having a second diameter larger than the first diameter;    a third insulating layer overlying the metal layer and in contact with the sidewalls of the second insulating layer and the metal layer, the third insulating layer including a third opening having a third diameter larger than the first diameter and smaller than the second diameter;    a passivating layer overlying the third insulating layer and extending into the third opening, the passivating layer including a fourth opening having a fourth diameter smaller than the second diameter and the third diameter and larger than the first diameter.    
     
     
         7 . The intermediate semiconductor device structure of  claim 6 , wherein the first insulating layer comprises silicon dioxide.  
     
     
         8 . The intermediate semiconductor device structure of  claim 6 , wherein the conductive layer comprises doped polysilicon.  
     
     
         9 . The intermediate semiconductor device structure of  claim 6 , wherein the second insulating layer and third insulating layer comprises silicon dioxide.  
     
     
         10 . The intermediate semiconductor device structure of  claim 6 , wherein the passivating layer comprises silicon nitride.  
     
     
         11 . The intermediate semiconductor device structure of  claim 6 , further comprising a polymer film plug in contact with the third insulating layer and extending to an edge of the fourth opening.

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