Semiconductor device including a floating gate electrode having stacked structure

Abstract

A semiconductor device includes a semiconductor layer having a plurality of element regions in its surface area, which are delimited by at least one element isolation trench, a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween and each including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width, and a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation films interposed therebetween. The device further includes an element isolating insulation film buried into the element isolation trench. The top surface of the element isolating insulation film is located higher than that of the first charge-storage layer.

1 . A semiconductor device comprising: 
 a semiconductor layer having a plurality of element regions in a surface area thereof, the element regions being delimited by at least one element isolation trench;    a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween, each of the floating gate electrodes including a first charge-storage layer having a first width which is equal to that of each of the element regions and a second charge-storage layer stacked on the first charge-storage layer and having a second width which is smaller than the first width;    a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation film interposed therebetween; and    an element isolating insulation film buried into the element isolation trench, a top surface of the element isolating insulation film being located higher than that of the first charge-storage layer.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the second charge-storage layer is a polysilicon layer formed by selective epitaxial growth.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein the second charge-storage layer is a polysilicon layer formed by chemical vapor deposition.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein the element isolation trench is provided along a first direction.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein the control gate electrodes are continuously provided in a second direction that crosses the element isolation trench.  
   
   
       6 . The semiconductor device according to  claim 1 , wherein nonvolatile memory cells are provided in surface areas of the element regions, respectively, which correspond to the floating gate electrodes and the control gate electrodes.  
   
   
       7 . The semiconductor device according to  claim 6 , wherein a given number of nonvolatile memory cells are arranged in series in the first direction to form a NAND type memory cell column.  
   
   
       8 . The semiconductor device according to  claim 1 , wherein a second distance between second charge-storage layers of adjacent two floating gate electrodes is longer than a first distance between first charge-storage layers.  
   
   
       9 . A semiconductor device comprising: 
 a semiconductor layer having at least one element isolation trench in a surface area thereof;    at least one element isolation region formed by burying an element isolating insulation film into the element isolation trench;    a plurality of element regions electrically isolated by the element isolation region;    a plurality of floating gate electrodes provided on the element regions with a first gate insulation film interposed therebetween; and    a plurality of control gate electrodes provided on the floating gate electrodes with a second gate insulation film interposed therebetween,    wherein the floating gate electrodes each have a stacked structure of two or more charge-storage layers, a width of a lowermost charge-storage layer being equal to that of each of the element regions, and a width of each of other upper charge-storage layers being smaller than that of the lowermost charge-storage layer, and a top surface of the lowermost charge-storage layer is located lower than that of the element isolating insulation film.    
   
   
       10 . The semiconductor device according to  claim 9 , wherein the upper charge-storage layers are polysilicon layers formed by selective epitaxial growth.  
   
   
       11 . The semiconductor device according to  claim 9 , wherein the upper charge-storage layers are polysilicon layer formed by chemical vapor deposition.  
   
   
       12 . The semiconductor device according to  claim 9 , wherein the element isolation trench is provided along a first direction.  
   
   
       13 . The semiconductor device according to  claim 9 , wherein the control gate electrodes are continuously provided in a second direction that crosses the element isolation trench.  
   
   
       14 . The semiconductor device according to  claim 9 , wherein nonvolatile memory cells are provided in surface areas of the element regions, respectively, which correspond to the floating gate electrodes and the control gate electrodes.  
   
   
       15 . The semiconductor device according to  claim 14 , wherein a given number of nonvolatile memory cells are arranged in series in the first direction to form a NAND type memory cell column.  
   
   
       16 . The semiconductor device according to  claim 9 , wherein a second distance between second charge-storage layers of adjacent two floating gate electrodes is longer than a first distance between first charge-storage layers.