Transistor having a germanium implant region located therein and a method of manufacture therefor

Abstract

The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100 , in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110 , wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

1 . A transistor device, comprising: 
 a polysilicon gate electrode located over a semiconductor substrate, wherein a sidewall of said polysilicon gate electrode has a germanium implanted region located therein; and    source/drain regions located within said semiconductor substrate proximate said polysilicon gate electrode.    
   
   
       2 . The transistor as recited in  claim 1  wherein multiple sidewalls of said polysilicon gate electrode have said germanium implanted region located therein.  
   
   
       3 . The transistor as recited in  claim 1  wherein said germanium implanted region has a thickness ranging from about 2 nm to about 15 nm.  
   
   
       4 . The transistor as recited in  claim 1  wherein each of said source/drain regions includes a lightly doped source/drain portion located under said polysilicon gate electrode by a distance X, and wherein said germanium implanted region has a thickness of less than X.  
   
   
       5 . The transistor as recited in  claim 1  wherein said polysilicon gate electrode has a P-type dopant located therein, and said germanium implanted region causes said P-type dopant to accumulate around said sidewall.  
   
   
       6 . The transistor as recited in  claim 1  wherein said germanium implanted region extends into an upper region of said source/drain regions.  
   
   
       7 . The transistor as recited in  claim 6  wherein said germanium implanted region extends from about 4 nm to about 10 nm into an upper region of said source/drain regions.  
   
   
       8 . The transistor as recited in  claim 1  further including a gate oxide located between said polysilicon gate electrode and said semiconductor substrate, wherein said germanium implanted region extends into a sidewall of said gate oxide.  
   
   
       9 . The transistor as recited in  claim 1  wherein said germanium implanted region has a dopant concentration ranging from about 2E21 atoms/cm 3  to about 8E21 atoms/cm 3 .  
   
   
       10 . An integrated circuit, comprising: 
 transistors located over a semiconductor substrate, wherein each of said transistors includes; 
 a polysilicon gate electrode located over said semiconductor substrate, wherein a sidewall of said polysilicon gate electrode has a germanium implanted region located therein; and  
 source/drain regions located within said semiconductor substrate proximate said polysilicon gate electrode; and  
   an interlevel dielectric layer located over said transistors, said interlevel dielectric layer having interconnects located therein for contacting said transistors to form an operational integrated circuit.    
   
   
       11 . The integrated circuit as recited in  claim 10  wherein said polysilicon gate electrode has a P-type dopant located therein, and said germanium implanted region causes said P-type dopant to accumulate around said sidewall.  
   
   
       12 . The integrated circuit as recited in  claim 10  wherein said transistors are selected from the group consisting of: 
 CMOS devices;    BiCMOS devices; and    bipolar devices.