Buffered continuous multi-drop clock ring

Abstract

A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a continuous free running clock that may be passed serially through a subset of memory units in the architecture. Sending of data is delayed over the point to point links based on proximity of the memory units to the buffer chip to accommodate delay in the multidrop clock signal.

1 . An apparatus comprising: 
 a plurality of memory units; and    a buffer to communicate over a plurality of point to point data lanes, one data lane to each of the plurality of memory units and to forward a continuous clock serially through each memory unit to drive the plurality of data lanes wherein the buffer comprises at least one time shifter.    
   
   
       2 . The apparatus of  claim 1  wherein the at least one time shifter comprises: 
 a plurality of time shifters to shift a timing of data transmitted on the point to point data lanes based on a proximity of the memory unit to the buffer.    
   
   
       3 . The apparatus of  claim 2  wherein each time shifter comprises: 
 a delay lock loop.    
   
   
       4 . The apparatus of  claim 1  wherein each memory unit comprises a dynamic random access memory.  
   
   
       5 . The apparatus of  claim 1  wherein each data lane is 8 bits wide.  
   
   
       6 . The apparatus of  claim 1  wherein the buffer comprises: a clock generator to provide a free running clock.  
   
   
       7 . A method comprising: 
 generating a continuous clock signal;    forwarding the clock signal serially through a plurality of memory units in decreasing proximity to a clock source; and    deskewing the clock signal relative to a data signal over a point to point link from a memory unit to the clock source.    
   
   
       8 . The method of  claim 7  further comprising: 
 supplying data to a memory unit over a point to point link in quadrature with the clock signal.    
   
   
       9 . The method of  claim 8  wherein the supply comprises: 
 delaying data delivery on a point to point link to a memory unit of the plurality based on proximity of the memory unit to the clock source.