Flash memory device for reducing error occurrence ratio in program operation and method of controlling program operation thereof

Abstract

A flash memory device and method of controlling a program operation thereof, includes page buffers divided into a predetermined number of groups and a program operation is performed on a group basis.

1 . A flash memory device, comprising: 
 a memory cell block including memory cells that share a plurality of groups of bit line pairs;    a plurality of groups of page buffers, wherein each group of page buffers is connected to a respective group of bit line pairs and is arranged to output program data to memory cells connected to part of the bit line pairs of corresponding groups in response to a program control signal; and    a program control unit arranged to consecutively generate the program control signal for each group of page buffers at a predetermined time distance during a program operation,    wherein during the program operation, while each of the page buffers of one of the plurality of groups of page buffers outputs the program data to the memory cells connected to any one of a corresponding bit line pair, the page buffers of the remaining groups of page buffers do not output the program data.    
   
   
       2 . The flash memory device of  claim 1 , wherein each of the plurality of groups of page buffers comprises a dual latch structure including at least one main latch and at least one cache latch.  
   
   
       3 . The flash memory device of  claim 1 , wherein the program control unit comprises: 
 a micro controller arranged to output an internal program signal in response to a program command;    a logic circuit arranged to output a first program control signal in response to the internal program signal;    a first delay circuit arranged to delay the first program control signal for a first setting time and arranged to output the signal delayed for the first setting time as a second program control signal;    a second delay circuit arranged to delay the first program control signal for a second setting time and arranged to output the signal delayed for the second setting time as a third program control signal; and    a third delay circuit arranged to delay the first program control signal for a third setting time and arranged to output the signal delayed for the third setting time as a fourth program control signal.    
   
   
       4 . The flash memory device of  claim 3 , wherein the third setting time is longer than the second setting time and the second setting time is longer than the first setting time.  
   
   
       5 . The flash memory device as claimed in  claim 3 , wherein each of the first to third delay circuits includes: 
 resistors connected in series; and    capacitors connected in parallel between the resistors,    wherein the number of the resistors and the capacitors included in the third delay circuit is greater than those included in the second delay circuit, and the number of the resistors and the capacitors included in the second delay circuit is greater than those include in the first delay circuit.    
   
   
       6 . A method of controlling a program control of a flash memory device, comprising: 
 storing first program data in a main latch of each of a plurality of groups of page buffers, wherein each group of page buffers is connected to a respective group of bit line pairs;    outputting an internal program signal in response to a program command;    consecutively generating a program control signal for each group of page buffers at a predetermined time distance in response to the internal program signal;    whenever one of the program control signals is generated, outputting first program data stored in page buffers of any one of the plurality of groups of page buffers to memory cells of a selected page connected to part of bit line pairs of any one of the groups of bit line pairs in response to the generated program control signal; and    while the program control signals are consecutively generated, outputting second program data to cache latches of each of the plurality of groups of page buffers.    
   
   
       7 . The method of  claim 6 , further comprising, prior to outputting the internal program signal: 
 supplying a program voltage to a word line to which the memory cells of the selected page are connected; and    connecting part of the plurality of groups of bit line pairs to sensing nodes of the plurality of groups of page buffers.    
   
   
       8 . The method of  claim 6 , wherein generating the program control signals comprises: 
 outputting the first program control signal in response to the internal program signal;    delaying the first program control signal for a first setting time and outputting the signal delayed for the first setting time as a second program control signal;    delaying the first program control signal for a second setting time and outputting the signal delayed for the second setting time as a third program control signal; and    delaying the first program control signal for a third setting time and outputting the signal delayed for the third setting time as a fourth program control signal.    
   
   
       9 . The method of  claim 6 , wherein the third setting time is longer than the second setting time and the second setting time is longer than the first setting time.