High performance integrated vertical transistors and method of making the same

Abstract

A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

1 . A semiconductor structure on a substrate comprising: 
 a downwards operating vertical NPN transistor formed on said substrate and having an epitaxial extrinsic base region, an emitter region, and a collector region, and    a downwards-operating vertical PNP transistor formed on said substrate having an epitaxial base region, an emitter region, and a collector region;    wherein said base region of said vertical NPN transistor comprises a first portion of a first layer and said base region of said vertical PNP transistor comprises a second portion of said first layer.    
   
   
       2 . The semiconductor structure of  claim 1 , wherein said first layer comprises epitaxial silicon germanium (SiGe).  
   
   
       3 . The semiconductor substrate of  claim 1 , wherein said epitaxial SiGe includes a first dopant type.  
   
   
       4 . The semiconductor substrate of  claim 3 , wherein said first dopant type includes a p-type dopant.  
   
   
       5 . The semiconductor substrate of  claim 1 , wherein a portion of said emitter of said PNP transistor comprises a portion of said second portion of said first layer.  
   
   
       6 . The semiconductor substrate of  claim 1 , wherein an intrinsic base of said NPN transistor comprises said first portion of said first layer.  
   
   
       7 . The semiconductor substrate of  claim 1 , wherein an extrinsic base of said NPN transistor comprises a first portion of a second layer and the emitter of said PNP transistor comprises a second portion of said second layer.  
   
   
       8 . The semiconductor substrate of  claim 7 , wherein said second layer comprises polysilicon or silicon.  
   
   
       9 . The semiconductor substrate of  claim 8 , wherein said polysilicon or silicon layer comprises a p-type dopant.  
   
   
       10 . A semiconductor structure on a substrate comprising a downwards operating vertical PNP transistor formed on said substrate having a base region, an emitter region, and a collector region wherein said collector region of said vertical PNP transistor is formed on a same layer on said substrate as a collector region for a downwards operating vertical NPN transistor.  
   
   
       11 . The semiconductor structure of  claim 10 , wherein said layer comprises epitaxial silicon germanium (SiGe).  
   
   
       12 . The semiconductor structure of  claim 10 , wherein said layer comprises an epitaxial silicon germanium (SiGe) layer or a silicon layer.  
   
   
       13 . The semiconductor substrate of  claim 10 , wherein said layer includes a first dopant type.  
   
   
       14 . The semiconductor substrate of  claim 13 , wherein said first dopant type includes a p-type dopant or an n-type dopant.  
   
   
       15 - 26 . (canceled)