Semiconductor device and manufacturing method thereof

Abstract

In a method for manufacturing an FET having a gate insulation film with an SiO 2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO 2 films, an SiO 2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO 2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

1 . A semiconductor device having a field effect transistor which comprises a gate electrode formed over a silicon substrate and a high dielectric gate insulation film formed between said gate electrode and said silicon substrate, said high dielectric gate insulation film comprising: 
 a metal oxide film having a higher dielectric constant than that of a silicon oxide film; and    a first silicon oxide film or a silicon oxysnitride film formed between said silicon substrate and said metal oxide film,    wherein said first silicon oxide film or said silicon oxynitride film has a thickness of 0.5 nm or more.    
   
   
       2 . A semiconductor device according to  claim 1 , 
 wherein said metal oxide film is a rare earth oxide layer made of one of Al 2 O 3 , ZrO 2 , HfO 2 , ZrSIO 4 , HfSiO 4 , Y 2 O 3  and La 2 O 3 , or a rare earth oxide layer made of one of ZrO 2 , HfO 2 , ZrSiO 4 , HfSiO 4 , Y 2 O 3  and La 2 O 3  formed on a Al 2 O 3  layer.    
   
   
       3 . A semiconductor device according to  claim 1 , 
 wherein said gate electrode comprises a polycrystalline silicon film,    wherein said high dielectric gate insulation film further comprises a second silicon oxide film formed between said metal oxide film and said polycrystalline silicon film, and    wherein said second silicon oxide film has a thickness of 0.5 nm or more.    
   
   
       4 . A semiconductor device according to  claim 1 , 
 wherein said gate electrode further comprises a high melting temperature metal film formed on said metal oxide film.