Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system

Abstract

Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from occurring are previously registered by registration means 511 as the cells to be registered in a cell library 505. Whether or not a wiring conductor conducting to a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device is determined by determination means 514 and if the wiring conductor exceeds the allowable antenna ratio, one or more repeater cells are inserted into any point of the wiring conductor by selection means 515.

1 . A semiconductor device formed by combining and placing previously registered functional blocks, and determining a wiring pattern spread over a plurality of wiring layers in accordance with given logical circuit specifications, 
 wherein each wiring conductor conducting to a gate electrode in each of the wiring layers, when a ratio between an area of the wiring conductor conducting to the gate electrode and an area of the gate electrode is assumed to be an antenna ratio, is limited to an area or wiring length such that the wiring conductor becomes an antenna ratio of less than a half an antenna ratio allowed essentially in said semiconductor device and is divided into at least three parts.    
   
   
       2 . A semiconductor device design method for forming a semiconductor device by combining and placing previously registered functional blocks, and determining a wiring pattern spread over a plurality of wiring layers in accordance with given logical circuit specifications, said design method comprising the step of: 
 limiting each wiring conductor to a gate electrode in each of the wiring layers, when a ratio between an area of the wiring conductor conducting to the gate electrode and an area of the gate electrode is assumed to be an antenna ratio, to an area or a wiring length such that the wiring conductor becomes an antenna ratio of less than a half an antenna ratio allowed essentially in said semiconductor device and dividing into at least three parts for wiring.    
   
   
       3 . A computer-readable recording medium storing the semiconductor device design method as claimed in  claim 2  as a program for causing a computer to execute the semiconductor device design method.  
   
   
       4 . A semiconductor device design support system for automatically forming a semiconductor device by combing and placing previously registered functional blocks, and determining a wiring pattern spread over a plurality of wiring layers in accordance with given logical circuit specifications, said design support system comprising: 
 means for limiting each wiring conductor conducting to a gate electrode in each of the wiring layers, when a ratio between an area of the wiring conductor conducting to the gate electrode and an area of the gate electrode is assumed to be an antenna ratio, to an area or a wiring length such that the wiring conductor becomes an antenna ratio of less that a half an antenna ratio allowed essentially in said semiconductor device and dividing into at least three parts for wiring.