Method of renaming registers in register file and microprocessor thereof

Abstract

A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue unit.

1 . A system for processing an instruction in a microprocessor, comprising: 
 a plurality of clusters having at least one functional unit for executing the instruction; and    a plurality of register files having a predetermined number of physical registers to and from which data is write and read in accordance with the instruction,    wherein each of the register files has one write port to which an output of a corresponding cluster is connected, and data write operation in accordance with the instruction executed by the at least one functional unit is performed by accessing the physical registers of the at least one register file, and wherein each of the plurality of register files has at least one read port from which any of the plurality of clusters can read data.    
     
     
         2 . The system of  claim 1 , wherein each of the plurality of clusters includes multiple functional units each for executing different instructions.  
     
     
         3 . The system of  claim 1 , further including means for renaming architected registers of the instruction with the physical registers of each of the plurality of register files.  
     
     
         4 . The system of  claim 3 , wherein the architected registers are target registers in which a result of the instruction is stored.  
     
     
         5 . The system of  claim 3 , further including at least one issue-queue unit associated with the plurality of clusters, for holding instruction renamed by the means for renaming until the instruction is issued to be executed in one of the plurality of clusters.