US2006292801A1PendingUtilityA1
Bit line of a semiconductor device and method for fabricating the same
Est. expiryJun 22, 2025(expired)· nominal 20-yr term from priority
Inventors:Jie Won Chung
H10W 20/074H10W 20/069H10D 64/011H10D 64/665
34
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Claims
Abstract
A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.
Claims
exact text as granted — not AI-modified1 . A bit line of a semiconductor device, comprising:
a first interlayer dielectric film disposed on a semiconductor substrate; a plurality of bit line stacks disposed on the first interlayer dielectric film; a plurality of bit line spacers disposed on side walls of the bit line stacks; and a buffer film disposed on the bit line spacers, the first interlayer dielectric film, and the bit line stacks.
2 . The bit line according to claim 1 , wherein the bit line stacks includes a tungsten film and a hard mask nitride film that are sequentially stacked.
3 . The bit line according to claim 1 , wherein the bit line spacers include a nitride film.
4 . A method for fabricating a bit line of a semiconductor device, comprising:
forming bit line stacks on a first interlayer dielectric film formed on a semiconductor substrate; forming bit line spacers on side walls of the bit line stacks; forming a buffer film on the first interlayer dielectric film and bit line stacks; annealing the buffer film to lower tensile stress thereof; and forming a second interlayer dielectric film on an entire surface of the resulting structure having the buffer film formed thereon.
5 . The method according to claim 4 , wherein the bit line stack-forming material includes a tungsten film and a hard mask nitride film sequentially stacked.
6 . The method according to claim 4 , wherein the bit line spacers include a nitride film.
7 . The method according to claim 4 , wherein the buffer film includes an oxide film formed via an atomic layer deposition (ALD) process utilizing pyridine as a catalyst.
8 . The method according to claim 4 , wherein annealing is carried out at a temperature of about 650° C. to 700° C. for about 120 seconds under nitrogen atmosphere.Join the waitlist — get patent alerts
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