Memory embedded semiconductor device and method for fabricating the same

Abstract

A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon. On the other hand, the memory transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon to be thinner than the silicide film formed on each of the source/drain diffusion layers of the logic transistor.

1 - 10 . (canceled)  
   
   
       11 . A method for fabricating a memory embedded semiconductor device comprising a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate, the method comprising the steps of: 
 (a) forming gate electrodes and source/drain diffusion layers of each of the memory transistor and the logic transistor in the semiconductor substrate;    (b) implanting ions of an impurity for suppressing a silicide reaction into at least the source/drain diffusion layers of the memory transistor by using an implant mask covering the logic region to form ion implanted regions; and    (c) after step (b), forming a first silicide film on each of the source/drain diffusion layers of the logic transistor and a second silicide film on each of the source/drain diffusion layers of the memory transistor,    wherein in step (c), an under side of a region where the second silicide film is formed on each of the source/drain diffusion layers of the memory transistor has the ion implanted regions, and    an under side of a region where the first silicide film is formed on each of the source/drain diffusion layers of the logic transistor has no ion implanted region.    
   
   
       12 . The method of  claim 11 , wherein the second silicide film has a thickness thinner than the first silicide film.  
   
   
       13 . The method of  claim 11 , wherein: 
 in step (a), polysilicon electrodes having exposed upper surfaces are formed as gate electrodes of each of the memory transistor and the logic transistor,    in step (b), ions of the impurity for suppressing a silicide reaction is also implanted in the polysilicon electrodes of the memory transistor,    in step (c), a third silicide film is formed on each of the polysilicon electrodes of the logic transistor and a fourth silicide film is formed on each of the polysilicon electrodes of the memory transistor.    
   
   
       14 . The method of  claim 13 , wherein the fourth silicide film has a thickness thinner than the third silicide film.  
   
   
       15 . The method of  claim 11 , wherein the ions of the impurity for suppressing a silicide reaction are ions of an impurity selected from nitrogen, argon, neon, arsenic, silicon, and germanium.  
   
   
       16 . The method of  claim 11 , wherein each of the ion implanted regions is an amorphous layer.  
   
   
       17 . The method of  claim 11 , wherein the memory region is random access memory or read only memory.  
   
   
       18 . A method for fabricating a memory embedded semiconductor device comprising a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate, the method comprising the steps of: 
 (a) forming gate electrodes and source/drain diffusion layers of each of the memory transistor and the logic transistor in the semiconductor substrate;    (b) forming an insulating film for suppressing a silicide reaction covering the memory region and having an opening over the logic region; and    (c) depositing a metal film over each of the logic region and the memory region with the insulating film for suppressing a silicide reaction being formed to form a first silicide film through silicidation on each of the source/drain diffusion layers of the logic transistor and a second silicide film through silicidation on each of the source/drain diffusion layers of the memory transistor.    
   
   
       19 . The method of  claim 18 , wherein the second silicide film has a thickness thinner than the first silicide film.  
   
   
       20 . The method of  claim 18 , wherein: 
 in step (a), polysilicon electrodes having exposed upper surfaces are formed as gate electrodes of each of the memory transistor and the logic transistor,    in step (b), the insulating film for suppressing a silicide reaction is also formed on each of the polysilicon electrodes of the memory transistor, and    in step (c), a third silicide film is formed on each of the polysilicon electrodes of the logic transistor and a fourth silicide film is formed on each of the polysilicon electrodes of the memory transistor.    
   
   
       21 . The method of  claim 20 , wherein the fourth silicide film has a thickness thinner than the third silicide film.  
   
   
       22 . The method of  claim 18 , wherein the insulating film for suppressing a silicide reaction is an oxide film.