Pre-patterned thin film capacitor and method for embedding same in a package substrate

Abstract

An embedded passive structure, its method of formation, and its intergration onto a substrate during fabrication are disclosed, In one embodiment the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.

1 . An embedded passive device in a substrate comprising: 
 a first conductive layer overlying a polymer build-up layer;    a dielectric layer overlying the first conductive layer;    a second conductive layer overlying the dielectric layer; and    a via that extends from the second conductive layer through the polymer build-up layer and electrically couples to an underlying interconnect, wherein the via extends through an opening patterned in the dielectric layer.    
   
   
       2 . The embedded passive device of  claim 1 , wherein: 
 the first conductive layer is further characterized as a first electrode layer;    the dielectric layer is further characterized as a capacitor dielectric layer;    the second conductive layer is further characterized a second electrode layer; and    a combination of the first electrode layer, the capacitor dielectric layer, and the second electrode layer forms an embedded capacitor structure in the substrate.    
   
   
       3 . The embedded passive device of  claim 2 , wherein the capacitor dielectric layer includes a ceramic dielectric material.  
   
   
       4 . The embedded passive device of  claim 3 , wherein the ceramic dielectric material is selected from the group consisting of strontium titinate, barium strontium titinate, and/or barium titinate.  
   
   
       5 . The embedded passive device of  claim 4 , wherein the substrate is further characterized as an organic substrate.  
   
   
       6 . The embedded passive device of  claim 5 , wherein a core of the substrate includes bismaleimide triazine resin.  
   
   
       7 . The embedded passive device of  claim 5 , wherein the second conductive layer comprises a material selected from the group consisting of copper and nickel.  
   
   
       8 . The embedded passive device of  claim 5 , wherein the first conductive layer comprises a material selected from a group consisting of copper, platinum, and nickel.  
   
   
       9 . The embedded passive device of  claim 3 , wherein the via extends through an opening patterned in the first conductive layer.  
   
   
       10 . An embedded passive laminate for applying to a substrate comprising: 
 a patterned electrode layer;    a patterned capacitor dielectric layer; and    an unpatterned electrode layer.    
   
   
       11 . The embedded passive laminate of  claim 10 , wherein the patterned electrode layer comprises a material selected from the group consisting of copper, platinum, and nickel.  
   
   
       12 . The embedded passive laminate of  claim 11 , wherein the unpatterned electrode layer comprises a material selected from the group consisting of copper and nickel.  
   
   
       13 . The embedded passive laminate of  claim 11 , wherein the patterned capacitor dielectric layer comprises a ceramic dielectric material.  
   
   
       14 . The embedded passive laminate of  claim 11 , wherein the patterned capacitor dielectric layer comprises a material selected from the group consisting of strontium titinate, barium strontium titinate, and/or barium titinate.  
   
   
       15 . The embedded passive laminate of  claim 14 , wherein the substrate is further characterized as an organic substrate.  
   
   
       16 . A method for forming embedded passive structures in an organic packaging substrate comprising affixing an embedded passive laminate on the organic packaging substrate, wherein the embedded passive laminate includes a pre-patterned capacitor dielectric layer.  
   
   
       17 . The method of  claim 16 , wherein the pre-patterned capacitor dielectric layer is further characterized as a ceramic dielectric material.  
   
   
       18 . The method of  claim 17 , wherein the ceramic dielectric material is further characterized as being selected from a group consisting of strontium titinate, barium strontium titinate, and/or barium titinate.  
   
   
       19 . The method of  claim 18 , wherein the substrate is further characterized as an organic substrate.  
   
   
       20 . A method for forming an embedded thin film capacitor comprising: 
 depositing a ceramic dielectric layer over a base layer of conductive material;    patterning the ceramic dielectric layer to form first openings that expose portions of the base layer;    depositing a lower electrode layer over the ceramic dielectric layer; and    patterning the lower electrode layer to form second openings that expose portions of the base layer.    
   
   
       21 . The method of  claim 20  further comprising heating the ceramic dielectric at a temperature in a range of 500-900 degrees Celsius. prior to depositing the lower electrode layer.  
   
   
       22 . The method of  claim 21 , wherein the combination base layer, patterned capacitor dielectric, and patterned lower electrode layer forms a thin film capacitor laminate, the method further comprising: 
 mounting the thin film capacitor laminate over a dielectric layer on a substrate, wherein the patterned lower electrode layer is positioned between the base layer and the dielectric layer;    removing portions of the base layer;    forming via openings that pass through the first opening and the second opening and that extend through the dielectric layer to an underlying conductive structure;    filling the via openings with a conductive material; and    patterning the conductive material to form a conductive structure.    
   
   
       23 . The method of  claim 22 , wherein the ceramic capacitor dielectric is further characterized as a material selected from a group consisting of strontium titinate, barium strontium titinate, and/or barium titinate.  
   
   
       24 . The method of  claim 23 , wherein the base layer includes at least one of copper and nickel.  
   
   
       25 . The method of  claim 24 , wherein the lower electrode layer includes at least one of copper, platinum, and nickel  
   
   
       26 . The method of  claim 23  wherein the first opening is wider than the second opening.  
   
   
       27 . The method of  claim 23 , wherein the second opening is wider than the first opening and wherein the conductive structure electrically couples to portions of the lower electrode layer.  
   
   
       28 . The method of  claim 23 , wherein the conductive structure is further characterized as an upper capacitor electrode.  
   
   
       29 . A method for packaging a semiconductor die comprising mounting the semiconductor die to an organic packaging substrate, wherein the organic packaging substrate includes embedded thin film capacitors that have been formed by applying a laminate that includes a pre-patterned capacitor dielectric layer over build-up layers of the packaging substrate.  
   
   
       30 . The method of  claim 29 , wherein the package substrate is further chartacterized as a ball grid array package substrate.