Method for forming raised structures by controlled selective epitaxial growth of facet using spacer

Abstract

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface. The resultant structure can function, for example, as a vertical gate of a DRAM cell, elevated source/drain structures, or other semiconductor device feature.

1 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising at least two overlying layers of epitaxial silicon including an uppermost epitaxial layer; each epitaxial silicon layer having an upper surface and sidewalls, and an insulative layer over the sidewalls of each epitaxial silicon layer and the upper surface of the uppermost epitaxial layer.    
   
   
       2 . The structure of  claim 1 , wherein each epitaxial silicon layer has a thickness of about 50-200 nm.  
   
   
       3 . The structure of  claim 1 , wherein one or more epitaxial silicon layers has a thickness of about 70-100 nm.  
   
   
       4 . The structure of  claim 1 , wherein each epitaxial silicon layer has a thickness of at least about 10-30 nm.  
   
   
       5 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising at least two overlying layers of epitaxial silicon including an uppermost epitaxial layer; each epitaxial silicon layer having an upper surface and sidewalls, an insulative layer over the sidewalls of each epitaxial silicon layer and the upper surface of the uppermost epitaxial layer, and at least one of the epitaxial silicon layers comprising a conductivity enhancing dopant.    
   
   
       6 . The transistor of  claim 5 , wherein the uppermost epitaxial silicon layer comprises a conductivity enhancing dopant.  
   
   
       7 . The transistor of  claim 5 , wherein at least one of the epitaxial silicon layers comprises a concentration gradient of the dopant.  
   
   
       8 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising at least two overlying layers of epitaxial silicon including an uppermost epitaxial layer; each epitaxial silicon layer having an upper surface and sidewalls, an insulative layer over the sidewalls of each epitaxial silicon layer and the upper surface of the uppermost epitaxial layer, and the uppermost epitaxial layer comprises a source region comprising a conductivity enhancing dopant.    
   
   
       9 . The semiconductor structure of  claim 8 , wherein the uppermost epitaxial layer is at about 10-30 nm thick.  
   
   
       10 . A semiconductor structure, comprising: 
 a gate situated on a substrate in a vertical orientation over a drain region, the gate comprising at least two overlying layers of epitaxial silicon including an uppermost epitaxial layer; each epitaxial silicon layer having an upper surface and sidewalls, an insulative layer over the sidewalls of each epitaxial silicon layer and the upper surface of the uppermost epitaxial layer, and at least the uppermost layer comprising a conductivity enhancing dopant; the structure being a component of a transistor.    
   
   
       11 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising two or more overlying layers of epitaxial silicon, each epitaxial silicon layer having an upper surface and insulated sidewalls, a first epitaxial silicon layer situated on the substrate, and a second epitaxial silicon layer situated on a horizontally oriented facet of the upper surface of the first epitaxial silicon layer; and an uppermost epitaxial silicon layer of the gate having an insulated upper surface.    
   
   
       12 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising:    a first layer of epitaxial silicon situated on the substrate, and comprising vertical sidewalls and an upper surface defining a plurality of facets including a facet in a horizontal plane orientation, with an insulative spacer overlying the sidewalls and the upper surface but not the horizontal plane oriented facet; and    a second layer of epitaxial silicon situated on the horizontal plane oriented facet of the upper surface of the first epitaxial silicon layer, and comprising vertical sidewalls and an upper surface, with an insulative spacer overlying the sidewalls and the upper surface.    
   
   
       13 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising:    a first layer of epitaxial silicon situated on the substrate, and comprising vertical sidewalls and an upper surface defining a plurality of facets including a facet in a horizontal plane orientation, with an insulative spacer overlying the sidewalls and the upper surface but not the horizontal plane oriented facet; and    a second layer of epitaxial silicon situated on the horizontal plane oriented facet of the upper surface of the first epitaxial silicon layer, and comprising vertical sidewalls and an upper surface defining a plurality of facets, with an insulative spacer overlying the sidewalls and the upper surface.    
   
   
       14 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising:    at least two overlying layers of epitaxial silicon, including an uppermost epitaxial silicon layer; each epitaxial silicon layer having vertical sidewalls, and an upper surface defining a plurality of facets including a facet in a horizontal plane orientation;    an insulative spacer overlying the sidewalls and the upper surface but not the horizontal plane oriented facet; and    an insulative layer overlying the horizontal plane oriented facet of the upper surface of the uppermost epitaxial silicon layer.    
   
   
       15 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising:    at least two overlying layers of epitaxial silicon, including an uppermost epitaxial silicon layer; each epitaxial silicon layer having vertical sidewalls, and an upper surface defining a plurality of facets in a (110) or (111) plane orientation and a facet in a (100) plane orientation;    an insulative spacer overlying the sidewalls and the (110) or (111) plane oriented facets but not the (100) plane oriented facet; and    an insulative layer overlying the (100) plane oriented facet of the upper surface of the uppermost epitaxial silicon layer.    
   
   
       16 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising:    at least two overlying layers of epitaxial silicon, including an uppermost epitaxial silicon layer; each epitaxial silicon layer having vertical sidewalls, and an upper surface defining a plurality of facets in an angled (110) or (111) plane orientation and a facet in a horizontal (100) plane orientation;    an insulative spacer overlying the sidewalls and the angled (110) or (111) plane oriented facets but not the horizontal (100) plane oriented facet; and    an insulative layer overlying the horizontal (100) plane oriented facet of the upper surface of the uppermost epitaxial silicon layer.    
   
   
       17 . A semiconductor structure, comprising: 
 an elevated gate situated over a drain region within a substrate, the gate comprising:    at least two overlying layers of epitaxial silicon, including an uppermost epitaxial silicon layer; each epitaxial silicon layer having vertical sidewalls, and an upper surface defining a plurality of facets in an angled plane orientation and a facet in a horizontal plane orientation;    an insulative spacer overlying the sidewalls and the angled plane oriented facets but not the horizontal plane oriented facet; and    an insulative layer overlying the horizontal plane oriented facet of the upper surface of the uppermost epitaxial silicon layer.