Semiconductor wafer package and manufacturing method thereof

Abstract

A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask is formed above the semiconductor wafer to expose the under bump metallurgy layers through each of the openings of the mask. Afterwards, a plurality of bump structures are disposed separately in the openings wherein each of the bump structures has a bump and a reinforced layer covering the bump. Finally, a reflow step is performed so that each of the reflowed bumps is connected to the corresponding under bump metallurgy layer and the reinforced layers are transformed into bump-reinforced collars to cover the under bump metallurgy layers and encompass the bumps. In addition, a semiconductor wafer package, which is formed by the manufacturing method, is provided.

1 - 9 . (canceled)  
   
   
       10 . A semiconductor wafer package, comprising: 
 a semiconductor wafer having an active surface, a plurality of bonding pads formed on the active surface, a passivation layer located above the semiconductor wafer and exposing the bonding pads and a plurality of under bump metallurgy layers formed on the bonding pads;    a plurality of reflowed bumps disposed on the under bump metallurgy layers; and    a plurality of bump-reinforced collars, the bump-reinforced collars encompassing the reflowed bumps and covering the under bump metallurgy layers, wherein each of the reflowed bumps is exposed out of the each bump-reinforced collar having an exposed portion with a height substantially the same with each other.    
   
   
       11 . The semiconductor wafer package of  claim 10 , wherein the reflowed bump is a solder bump.  
   
   
       12 . The semiconductor wafer package of  claim 10 , wherein the bump-reinforced collar is made of a polymer material.  
   
   
       13 . The semiconductor wafer package of  claim 10 , wherein the passivation layer is made of a material selected from silicon nitride, phosphosilicate glass and silicon oxide.  
   
   
       14 . The semiconductor wafer package of  claim 10 , wherein each of the under bump metallurgy layers comprises a titanium layer, a nickel-vanadium layer and a copper layer.  
   
   
       15 . The semiconductor wafer package of  claim 10 , wherein the height of the exposed portion of the reflowed bump is at least equal to the first-six of the height of the reflowed bump.  
   
   
       16 . The semiconductor wafer package of  claim 10 , wherein the height of the exposed portion of reflowed bumps is more than the first-six of the height of the reflowed bump.  
   
   
       17 . The semiconductor wafer package of  claim 10 , wherein said each reflowed bump is a gold bump.  
   
   
       18 . The semiconductor wafer package of  claim 10 , wherein each of the under bump metallurgy layers is made of a material selected from titanium, titanium-tungsten alloy, aluminum, aluminum-nickel, nickel-vanadium, chromium-copper alloy, copper and nickel-vanadium.  
   
   
       19 . The semiconductor wafer package of  claim 10 , wherein the reflowed bumps are located over the bonding pads.  
   
   
       20 . The semiconductor wafer package of  claim 10 , wherein one of the under bump metallurgy layers is extended over the active surface of the semiconductor wafer.