Semiconductor device including bit line formed using damascene technique and method of fabricating the same

Abstract

A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

1 . A semiconductor device comprising: 
 an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening;    a bit line conductive layer that wholly or partially fills the narrow opening;    a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer; and    spacers formed on inner walls of the wide opening.    
   
   
       2 . The device of  claim 1 , wherein the bit line conductive layer includes a Ti layer, a TiN layer, and a W layer, which are inwardly and sequentially stacked.  
   
   
       3 . The device of  claim 1 , wherein an interface between the spacers and the insulating layer is flat.  
   
   
       4 . A semiconductor device comprising: 
 an insulating layer having an opening;    a conductive layer that partially fills the opening;    an insulative capping layer formed over the conductive layer in the opening; and    spacers formed on inner walls of the opening.    
   
   
       5 . The semiconductor device of  claim 4 , wherein the opening includes a first opening overlapping a second opening, the first opening being wider than the second opening.  
   
   
       6 . The semiconductor device of  claim 5 , wherein the conductive layer partially or completely fills the second opening and is formed below the spacers.  
   
   
       7 . The semiconductor device of  claim 4 , wherein the capping layer fills the first opening so that a top surface of the capping layer is level with a top surface of the insulating layer.  
   
   
       8 . The semiconductor device of  claim 4 , wherein the conductive layer is a bit line conductive layer.  
   
   
       9 . The semiconductor device of  claim 4 , wherein the capping layer is a bit line capping layer.