Method and apparatus for processor emulation

Abstract

An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller. The control circuitry, when connected to the emulation controller, effects the providing and receiving of signals and the transferring of serial data between the emulation controller and the emulator continuously without interruption while the first state machine remains in one state.

1 . An emulator for emulating the operation of data processing circuitry normally connected to and cooperable with a peripheral circuit, comprising: 
 serial scanning circuitry connectable to the peripheral circuit for, when connected to the peripheral circuit, providing to and receiving from the peripheral circuit signals which would normally be provided and received by the data processing circuitry during normal cooperation between the data processing circuitry and the peripheral circuit, said serial scanning circuitry being connectable to an emulation controller for providing serial data transfer between the emulation controller and the emulator; and    control circuitry connected to said serial scanning circuitry and connectable to the emulation controller for, when connected to the emulation controller, effecting said providing and receiving of signals while serial data is being continuously transferred without interruption between the test controller and said serial scanning circuitry.