Method and structure of an auxiliary transistor arrangement used for fabricating a semiconductor memory device

Abstract

Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.

1 . A semiconductor device comprising: 
 a doped zone that adjoins a section of a semiconductor substrate surface and is doped with a dopant of a first conduction type;    a gate dielectric provided over a portion of the section of the semiconductor substrate surface;    a gate conductor at least partially overlying the gate dielectric; and    a protective structure formed in the doped zone, the protective structure comprising at least two diodes coupled oppositely in series.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the at least two diodes are arranged perpendicular to the section of the semiconductor substrate surface.  
   
   
       3 . The semiconductor device of  claim 2 , wherein the at least two diodes are formed from a doped region that is arranged at a distance from the section of the semiconductor substrate surface and is doped with a dopant of a second conduction type opposite to the first conduction type.  
   
   
       4 . The semiconductor device of  claim 3 , wherein the doped region adjoins isolation trenches that are provided in the semiconductor substrate and adjoin the doped zone.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the at least two diodes coupled oppositely in series are formed from a second doped region that is arranged at a distance from the section of the semiconductor substrate surface and is doped with a second dopant of a second conduction type opposite to the first conduction type.  
   
   
       6 . The semiconductor device of  claim 5 , wherein the spatial extent of the second doped region is provided such that the second doped region adjoins isolation trenches that are provided in the semiconductor substrate and adjoin the doped zone.  
   
   
       7 . The semiconductor device of  claim 1 , wherein the protective structure prevents a leakage current path from arising between the gate conductor and doped zone.  
   
   
       8 . The semiconductor device of  claim 1 , wherein the gate conductor comprises a conductive layer on the gate dielectric and on the doped zone adjoining the section of the semiconductor substrate surface.  
   
   
       9 . The semiconductor device of  claim 1 , wherein the gate dielectric comprises a gate oxide.  
   
   
       10 . A semiconductor device, comprising: 
 a doped region that adjoins a section of a substrate surface and is doped with a dopant of a first conduction type;    a gate dielectric provided over a portion of the section of the substrate surface;    a conductive layer at least partially overlying the gate dielectric; and    a protective structure formed in the doped region and extending between two isolation trenches and adjoining the isolation trenches.    
   
   
       11 . The semiconductor device of  claim 10 , wherein the protective structure serves for preventing a leakage current path from arising between a gate conductor and the doped region.  
   
   
       12 . The semiconductor device of  claim 10 , wherein the protective structure comprises at least two diodes.  
   
   
       13 . The semiconductor device of  claim 12 , wherein the at least two diodes are arranged oppositely in a series perpendicular to the substrate surface.  
   
   
       14 . The semiconductor device of  claim 10 , wherein the protective structure comprises a second doped region located at a distance from the section of the substrate surface, the second doped region extending between the two isolation trenches and adjoining the isolation trenches and being doped with a dopant of a second conduction type opposite to the first conduction type.  
   
   
       15 . The semiconductor device of  claim 14 , wherein the protective structure serves to prevent a leakage current path from arising between a gate conductor and the doped region.  
   
   
       16 . The semiconductor device of  claim 10 , wherein the gate dielectric comprises a gate oxide.  
   
   
       17 . A semiconductor memory device, comprising: 
 a first region of a semiconductor substrate;    an array of memory cells in the first region;    a second region of the semiconductor substrate, the second region being adjacent the first region and being doped to a first conduction type at least at a surface;    a gate dielectric over a portion of the second region;    a gate conductor over the gate dielectric; and    a doped region within the second region and spaced from the surface, the doped region forming at least two diodes connected oppositely in series.    
   
   
       18 . The device of  claim 17 , wherein the doped region within the second region forms a protective structure for preventing a leakage current path from arising between the gate conductor and the first region of the substrate.  
   
   
       19 . The device of  claim 17 , wherein the doped region comprises a counter-doped region.  
   
   
       20 . The device of  claim 17 , wherein the doped region adjoins isolation trenches disposed in the semiconductor substrate.