Pulse Output Circuit, Shift Register and Electronic Equipment

Abstract

A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105 . An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

1 . A pulse output circuit comprising: 
 a first input terminal;    a second input terminal;    a third input terminal;    a first output terminal;    a first transistor having: 
 a first electrode electrically connected to the first input terminal;  
 a second electrode electrically connected to the first output terminal; and  
   a first gate electrode; 
 a second transistor having:  
 a third electrode electrically connected to a first power source;  
 a fourth electrode electrically connected to the first output terminal; and  
 a second gate electrode;  
   a first amplitude compensation circuit having: 
 a fourth input terminal electrically connected to the third input terminal;  
 a fifth input terminal electrically connected to the second input terminal; and  
 a second output terminal electrically connected to the second gate electrode; and  
   a second amplitude compensation circuit having: 
 a sixth input terminal electrically connected to the second input terminal;  
 a seventh input terminal electrically connected to the second output terminal; and  
 a third output terminal electrically connected to the first gate electrode,  
   wherein the first transistor and the second transistor have a same conductivity type.    
   
   
       2 . A pulse output circuit comprising: 
 a first input terminal;    a second input terminal;    a third input terminal;    a first output terminal;    a first transistor having: 
 a first electrode electrically connected to the first input terminal;  
 a second electrode electrically connected to the first output terminal; and  
 a first gate electrode;  
   a second transistor having: 
 a third electrode electrically connected to a first power source;  
 a fourth electrode electrically connected to the first output terminal; and  
 a second gate electrode;  
   a first amplitude compensation circuit having: 
 a fourth input terminal electrically connected to the third input terminal;  
 a fifth input terminal electrically connected to the second input terminal; and  
 a second output terminal electrically connected to the second gate electrode;  
   a second amplitude compensation circuit having: 
 a sixth input terminal electrically connected to the second input terminal;  
 a seventh input terminal electrically connected to the second output terminal; and  
 a third output terminal electrically connected to the first gate electrode,  
   a eighth input terminal; and    a third transistor having: 
 a fifth electrode electrically connected to a second power source;  
 a sixth electrode electrically connected to the second gate electrode; and  
 a third gate electrode electrically connected to the eighth input terminal,  
   wherein the first thin transistor, the second transistor, the third transistor have a same conductivity type.    
   
   
       3 . A pulse output circuit comprising: 
 first to third input terminals;    an output terminal;    a first transistor including a first electrode electrically connected to the first input terminal;    a second transistor including a first electrode electrically connected to a first power source;    a third transistor including a first electrode electrically connected to either a second power source or a gate electrode thereof;    a fourth transistor including a first electrode electrically connected to the first power source;    a fifth transistor including a first electrode electrically connected to the second power source; and    a sixth transistor including a first electrode electrically connected to the first power source,    wherein the first to sixth transistors have a same conductivity type;    each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;    each of a second electrode of the third transistor and a second electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;    each of a second electrode of the fifth transistor and a second electrode of the sixth transistor is electrically connected to a gate electrode of the second transistor and a gate electrode of the fourth transistor;    each of a gate electrode of the third transistor and a gate electrode of the sixth transistor is electrically connected to the second input terminal; and    a gate electrode of the fifth transistor is electrically connected to the third input terminal.    
   
   
       4 . A pulse output circuit comprising: 
 first to fourth input terminals;    an output terminal;    a first transistor including a first electrode electrically connected to the first input terminal;    a second transistor including a first electrode electrically connected to a first power source;    a third transistor including a first electrode electrically connected to either a second power source or a gate electrode thereof;    a fourth transistor including a first electrode electrically connected to the first power source;    a fifth transistor including a first electrode electrically connected to the second power source;    a sixth transistor including a first electrode electrically connected to the first power source; and    a seventh transistor including a first electrode electrically connected to the second power source,    wherein the first to seventh transistors have a same conductivity type;    each of a second electrode of the first transistor and a second electrode of the second transistor is electrically connected to the output terminal;    each of a second electrode of the third transistor and a second electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor;    each of a second electrode of the fifth transistor, a second electrode of the sixth transistor and a second electrode of the seventh transistor is electrically connected to a gate electrode of the second transistor and to a gate electrode of the fourth transistor;    each of a gate electrode of the third transistor and a gate electrode of the sixth transistor is electrically connected to the second input terminal;    a gate electrode of the fifth transistor is electrically connected to the third input terminal; and    a gate electrode of the seventh transistor is electrically connected to the fourth input terminal.    
   
   
       5 . A pulse output circuit according to  claim 3 , comprising a seventh transistor, 
 wherein a gate electrode of the seventh transistor is electrically connected to the second power source; and    the seventh transistor is provided between an output electrode of the third transistor and the gate electrode of the first transistor.    
   
   
       6 . A pulse output circuit according to  claim 4 , comprising an eighth transistor, 
 wherein a gate electrode of the eighth transistor is electrically connected to the second power source; and    the eighth transistor is provided between an output electrode of the third transistor and the gate electrode of the first transistor.    
   
   
       7 . A pulse output circuit according to  claim 3 , comprising: 
 a seventh transistor including a first electrode connected to a gate electrode thereof; and    an eighth transistor including a first electrode electrically connected to the first power source,    wherein the seventh transistor is provided between an output electrode of the third transistor and the gate electrode of the first transistor;    a gate electrode of the eighth transistor is electrically connected to each of the gate electrode of the second transistor and the gate electrode of the fourth transistor; and    a second electrode of the eighth transistor is electrically connected to the gate electrode of the first transistor.    
   
   
       8 . A pulse output circuit according to  claim 4 , comprising: 
 an eighth transistor including a first electrode connected to a gate electrode thereof; and    a ninth transistor including a first electrode electrically connected to the first power source,    wherein the eighth transistor is provided between an output electrode of the third transistor and the gate electrode of the first transistor;    a gate electrode of the ninth transistor is electrically connected to each of the gate electrode of the second transistor and the gate electrode of the fourth transistor; and    a second electrode of the ninth transistor is electrically connected to the gate electrode of the first transistor.    
   
   
       9 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 1 .  
   
   
       10 . An electronic equipment using a pulse output circuit according to  claim 1 .  
   
   
       11 . An electronic equipment using a shift register according to  claim 9 .  
   
   
       12 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 2 .  
   
   
       13 . An electronic equipment using a pulse output circuit according to  claim 2 .  
   
   
       14 . An electronic equipment using a shift register according to  claim 12 .  
   
   
       15 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 3 .  
   
   
       16 . An electronic equipment using a pulse output circuit according to  claim 3 .  
   
   
       17 . An electronic equipment using a shift register according to  claim 15 .  
   
   
       18 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 4 .  
   
   
       19 . An electronic equipment using a pulse output circuit according to  claim 4 .  
   
   
       20 . An electronic equipment using a shift register according to  claim 18 .  
   
   
       21 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 5 .  
   
   
       22 . An electronic equipment using a pulse output circuit according to  claim 5 .  
   
   
       23 . An electronic equipment using a shift register according to  claim 21 .  
   
   
       24 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 6 .  
   
   
       25 . An electronic equipment using a pulse output circuit according to  claim 6 .  
   
   
       26 . An electronic equipment using a shift register according to  claim 24 .  
   
   
       27 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 7 .  
   
   
       28 . An electronic equipment using a pulse output circuit according to  claim 7 .  
   
   
       29 . An electronic equipment using a shift register according to  claim 27 .  
   
   
       30 . A shift register comprising a plurality of stages of a pulse output circuit according to  claim 8 .  
   
   
       31 . An electronic equipment using a pulse output circuit according to  claim 8 .  
   
   
       32 . An electronic equipment using a shift register according to  claim 30 .  
   
   
       33 . A pulse output circuit according to  claim 16 , 
 wherein the eighth input terminal is selectively connected to any one of the fourth output terminal and the fifth input terminal, and    wherein the ninth input terminal is selectively connected to the other one of the fourth output terminal and the fifth input terminal.