Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same

Abstract

A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region.

1 . A Metal Oxide Semiconductor (MOS) Field Effect Transistor having a trench isolation region comprising: 
 a semiconductor substrate;    the trench isolation region disposed in a predetermined portion of the semiconductor substrate to define an active region;    a source region and a drain region spaced apart from each other within the active region with a channel region disposed between said source region and said drain region;    a gate electrode crossing over the channel region disposed between the source region and the drain region;    a gate insulating layer disposed between the gate electrode and the channel region; and    an edge insulating layer thicker than the gate insulating layer and disposed on a lower surface of the gate electrode around a boundary of the trench isolation region and the active region.    
   
   
       2 . The MOS Field Effect Transistor of  claim 1 , wherein the edge insulating layer comprises a plurality of layers.  
   
   
       3 . The MOS Field Effect Transistor of  claim 2 , wherein an uppermost layer of the edge insulating layer and the gate insulating layer are each composed of an identical material.  
   
   
       4 . The MOS Field Effect Transistor of  claim 2 , wherein the edge insulating layer comprises a lower oxide layer, an intermediary insulating, layer and an upper oxide layer.  
   
   
       5 . The MOS Field Effect Transistor of  claim 4 , wherein the intermediary insulating layer is composed of a material selected from a group consisting of nitride, aluminum oxide and tantalum oxide.  
   
   
       6 . The MOS Field Effect Transistor of  claim 1 , wherein the edge insulating layer is wider than the gate electrode on the boundary of the trench isolation region and the active region.  
   
   
       7 . The MOS Field Effect Transistor of  claim 1 , wherein the trench isolation region comprises a nitride liner.  
   
   
       8 . The MOS Field Effect Transistor of  claim 1 , wherein a thickness of the gate insulating layer is about 150 to about 2000 Å, and a thickness of the edge insulating layer is about 200 to about 10000 Å.  
   
   
       9 . A method of fabricating a Metal Oxide Semiconductor (MOS) Field Effect Transistor having a trench isolation region comprising: 
 forming the trench isolation region in a predetermined portion of a semiconductor substrate to define an active region;    forming a first insulating layer pattern that covers at least a boundary of the trench isolation region and the active region and exposes a channel region of the transistor;    forming a second insulating layer on at least substantially an entire surface of the semiconductor substrate where the first insulating layer pattern is formed; and    forming a gate electrode on at least substantially an entire surface of the semiconductor substrate where the second insulating layer and first insulating layer pattern have been formed and wherein the gate electrode crosses over the boundary of the trench isolation region and the active region.    
   
   
       10 . The method of  claim 9 , wherein the portion stacked with the first insulating layer and the second insulating layer is thicker than the second insulating layer.  
   
   
       11 . The method of  claim 9 , wherein the first insulating layer pattern comprises a plurality of layers  
   
   
       12 . The method of  claim 11 , wherein an uppermost layer of the first insulating layer pattern and the second insulating layer are each composed of an identical material.  
   
   
       13 . The method of  claim 11 , wherein the first insulating layer pattern comprises a lower oxide layer and an intermediary insulating layer.  
   
   
       14 . The method of  claim 13 , wherein the intermediary insulating layer is composed of a material selected from a group consisting of nitride, aluminum oxide and tantalum oxide.  
   
   
       15 . The method of  claim 9 , further comprising: after forming the trench isolation region, forming a source region and a drain region spaced apart from each other within the active region.  
   
   
       16 . The method of  claim 9 , further comprising: after forming the gate electrode, forming a source region and a drain region spaced apart from each other within the active region.  
   
   
       17 . The method of  claim 9 , wherein the trench isolation region is formed using a gap-fill insulating material selected from the group consisting of an oxide and a nitride liner.  
   
   
       18 . The method of  claim 15 , wherein the source region and the drain region are formed in the active region using ion implantation at a low density.  
   
   
       19 . The method of  claim 16 , wherein the source region and the drain region are formed in the active region using ion implantation at a low density.  
   
   
       20 . The method of  claim 9 , wherein the first insulating layer pattern and the second insulating layer each have a thickness of about 50 to about 500 Å.