Floating gate structures

Abstract

Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , Y 2 O 3 , Gd 2 O 3 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 . The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

1 . A floating gate transistor, comprising: 
 a first source/drain region and a second source drain region spaced apart from the first source/drain region;    a channel region interposed between the first source drain/region and the second source/drain region;    a floating gate structure positioned proximate to the channel region and spaced apart from the channel region by a gate oxide layer; and    a control gate structure positioned proximate to the floating gate structure and separated from the floating gate structure by a low tunnel barrier intergate dielectric layer having a tunnel barrier of less than approximately 1.5 eV.    
   
   
       2 . The floating gate transistor of  claim 1 , wherein the low tunnel barrier intergate dielectric layer further comprises one of a selected oxide of nickel and a selected oxide of aluminum.  
   
   
       3 . The floating gate transistor of  claim 1 , wherein the low tunnel barrier intergate dielectric layer further comprises a selected oxide of a transition metal.  
   
   
       4 . The floating gate transistor of  claim 3 , wherein the selected oxide of a transition metal comprises a selected oxide of tantalum, titanium, zirconium, niobium, yttrium and gadolinium.  
   
   
       5 . The floating gate transistor of  claim 1 , wherein the low tunnel barrier intergate dielectric layer further comprises a perovskite material.  
   
   
       6 . The floating gate transistor of  claim 5 , wherein the perovskite material comprises at least one of SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3  and PbZrO 3 .  
   
   
       7 . The floating gate transistor of  claim 1 , wherein the low tunnel barrier intergate dielectric layer further comprises a low tunnel barrier intergate dielectric layer having a thickness of less than approximately 20 Angstroms.  
   
   
       8 . The floating gate transistor of  claim 1 , wherein the first source/drain region and the second source/drain region further comprise an n-doped region.  
   
   
       9 . The floating gate transistor of  claim 1 , further comprising a first metal layer adjacent the floating gate structure and a second metal layer adjacent the control gate structure so that the a low tunnel barrier intergate dielectric layer is positioned between the first metal layer and the second metal layer.  
   
   
       10 . The floating gate transistor of  claim 9 , wherein the first metal layer and the second metal layer further comprise one of a platinum layer and an aluminum layer.  
   
   
       11 . The floating gate transistor of  claim 1 , wherein the floating gate structure and the control gate structure are comprised of polysilicon.  
   
   
       12 . The floating gate transistor of  claim 1 , wherein the first source/drain region is coupled to a source line of the memory device, the second source/drain layer is coupled to a bit line of the memory device, and the control gate is coupled to a control line of the memory device.  
   
   
       13 . A memory cell for a non-volatile memory device, comprising: 
 a first source/drain region and a second source drain region spaced apart from the first source/drain region;    a channel region positioned between the first source drain/region and the second source/drain region;    a polysilicon floating gate structure positioned proximate to the channel region and spaced apart from the channel region by a gate oxide layer;    a polysilicon control gate structure positioned proximate to the polysilicon floating gate structure; and    a low tunnel barrier intergate dielectric layer having a tunnel barrier of less than approximately 1.5 eV that is positioned between the polysilicon floating gate structure and the polysilicon control gate structure, wherein the low tunnel barrier intergate dielectric layer includes metal layers formed on opposing sides of the intergate dielectric layer.    
   
   
       14 . The memory cell of  claim 13 , wherein the low tunnel barrier intergate dielectric layer further comprises one of a nickel oxide dielectric layer and an aluminum oxide dielectric layer.  
   
   
       15 . The memory cell of  claim 13 , wherein the low tunnel barrier intergate dielectric layer further comprises a transition metal oxide layer.  
   
   
       16 . The memory cell of  claim 15 , wherein the transition metal oxide layer comprises a selected oxide of tantalum, titanium, zirconium, niobium, yttrium and gadolinium.  
   
   
       17 . The memory cell of  claim 13 , wherein the low tunnel barrier intergate dielectric layer further comprises a layer of a perovskite material, including one of SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3  and PbZrO 3 .  
   
   
       18 . The memory cell of  claim 13 , wherein the low tunnel barrier intergate dielectric layer further comprises a low tunnel barrier intergate dielectric layer having a thickness of less than approximately 20 Angstroms.  
   
   
       19 . The memory cell of  claim 13 , wherein the metal layers further comprise one of a platinum layer and an aluminum layer.  
   
   
       20 . The memory cell of  claim 13 , wherein the first source/drain region is coupled to a source line of the memory device, the second source/drain layer is coupled to a bit line of the memory device, and the control gate is coupled to a control line of the memory device.  
   
   
       21 . A memory structure for a non-volatile memory device, comprising: 
 a plurality of memory cells arranged in an array, wherein at least one of the plurality of memory cells further comprises: 
 a first source/drain region and a second source drain region spaced apart from the first source/drain region;  
 a channel region interposed between the first source drain/region and the second source/drain region;  
 a floating gate structure positioned proximate to the channel region and spaced apart from the channel region by a gate oxide layer;  
 a control gate structure positioned proximate to the floating gate structure; and  
 a low tunnel barrier intergate dielectric layer having a tunnel barrier of less than approximately 1.5 eV that is positioned between the polysilicon floating gate structure and the polysilicon control gate structure, wherein a source line of the array is coupled to the first source/drain region, a bit line of the array is coupled to the second source/drain layer, and a control line of the array is coupled to the control gate.  
   
   
   
       22 . The memory structure of  claim 21 , wherein the low tunnel barrier intergate dielectric layer further comprises one of a nickel oxide dielectric layer and an aluminum oxide dielectric layer.  
   
   
       23 . The memory structure of  claim 21 , wherein the low tunnel barrier intergate dielectric layer further comprises a transition metal oxide layer.  
   
   
       24 . The memory structure of  claim 23 , wherein the transition metal oxide layer comprises a selected oxide of tantalum, titanium, zirconium, niobium, yttrium and gadolinium.  
   
   
       25 . The memory structure of  claim 21 , wherein the low tunnel barrier intergate dielectric layer further comprises a layer of a perovskite material.  
   
   
       26 . The memory structure of  claim 25 , wherein the layer of a perovskite material comprises at least one of SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3  and PbZrO 3 .  
   
   
       27 . The memory structure of  claim 21 , wherein the low tunnel barrier intergate dielectric layer further comprises a low tunnel barrier intergate dielectric layer having a thickness of less than approximately 20 Angstroms.  
   
   
       28 . The memory structure of  claim 21 , further comprising a first metal layer adjacent the floating gate structure and a second metal layer adjacent the control gate structure so that the a low tunnel barrier intergate dielectric layer is positioned between the first metal layer and the second metal layer.  
   
   
       29 . The memory structure of  claim 28 , wherein the first metal layer and the second metal layer further comprise one of a platinum layer and an aluminum layer.  
   
   
       30 . The memory structure of  claim 21 , wherein the floating gate structure and the control gate structure are comprised of polysilicon.