Phase change RAM device and method for manufacturing the same

Abstract

A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.

1 . A phase change Random Access Memory (RAM) device comprising: 
 a semiconductor substrate having a phase change cell area and a voltage application area;    a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate;    a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area;    a second plug formed in the first oxide layer and the nitride layer of the voltage application area;    a conductive line formed in the second oxide layer on the second plug of the voltage application area;    a third oxide layer formed on the second oxide layer including the first plug and the conductive line;    a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug in the third oxide layer of the phase change cell area; and    a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.    
   
   
       2 . The phase change RAM device as claimed in  claim 1 , wherein the phase change cell area corresponds to a drain area of a transistor, and the voltage application area corresponds to a source area of the transistor.  
   
   
       3 . The phase change RAM device as claimed in  claim 1 , wherein the first plug, the second plug and the conductive line are made from tungsten.  
   
   
       4 . The phase change RAM device as claimed in  claim 1 , wherein the lower electrode is made from one of TiN, TiW, Al, Cu and Wsi.  
   
   
       5 . The phase change RAM device as claimed in  claim 1 , wherein the phase change layer is made from one of Ge—Sb—Te, Ge—Bi—Te, Sb—Te dope with at least one of Ag, In and Bi, and Bi—Te dope with at least one of Ag, In and Sn.  
   
   
       6 . The phase change RAM device as claimed in  claim 1 , wherein the upper electrode is made from one of Al, Ti, Ta, TaSiN, TaN, Ru, TiN, TiW and TiAlN.  
   
   
       7 . A method for manufacturing a phase change Random Access Memory (RAM) device, the method comprising the steps of: 
 providing a semiconductor substrate, the semiconductor substrate having an isolation layer for isolating an active area, a gate formed on the active area, and source and drain areas formed under a substrate surface on both sides of the gate;    sequentially forming a first oxide layer, a nitride layer and a second oxide layer on an entire surface of the semiconductor substrate;    etching the second oxide layer using the nitride layer as an etch stopping layer, thereby forming a trench shaped like a bar on the second oxide layer above the source area;    etching the first oxide layer, the nitride layer and the second oxide layer, thereby forming a first contact hole for exposing the drain area and a second contact hole for exposing the source area in a lower surface of the trench;    filling in a conductive layer within the first contact hole, the second contact hole, and the trench, thereby forming a first plug making contact with the drain area in the first contact hole, forming a second plug making contact with the source area in the second contact hole, and forming a conductive line in the trench;    forming a third oxide layer on the second oxide layer including the first plug and the conductive line;    forming a lower electrode shaped like a plug, the lower electrode directly making contact with the first plug in the third oxide layer above the drain area; and    sequentially forming a phase change layer and an upper electrode on the lower electrode and the third oxide layer in a pattern form, the third oxide layer being adjacent to the lower electrode.    
   
   
       8 . The method as claimed in  claim 7 , wherein the first plug, the second plug and the conductive line are made from tungsten.  
   
   
       9 . The method as claimed in  claim 7 , wherein the lower electrode is made from one of TiN, TiW, Al, Cu and Wsi.  
   
   
       10 . The method as claimed in  claim 7 , wherein the phase change layer is made from one of Ge—Sb—Te, Ge—Bi—Te, Sb—Te dope with at least one of Ag, In and Bi, and Bi—Te dope with at least one of Ag, In and Sn.  
   
   
       11 . The method as claimed in  claim 7 , wherein the upper electrode is made from one of Al, Ti, Ta, TaSiN, TaN, Ru, TiN, TiW and TiAlN.