Mechanism for storing and extracting trace information using internal memory in microcontrollers

Abstract

It is the object of the present invention to provide a mechanism to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. The on-chip debug logic includes a low speed debug port and a mechanism for temporarily storing trace data on the memory, wherein the trace data can be retrieved via the low speed debug port by a debug tool. A method and system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.

1 . A microcontroller comprising: 
 a microprocessor;    a memory device accessible through a data bus and an address bus coupled to the microprocessor;    on-chip debug logic coupled to the microprocessor; the on-chip debug logic including a low speed debug port; and a mechanism for temporarily storing trace data on the memory, wherein the trace data can be retrieved via the debug port by a debug tool.    
     
     
         2 . The microcontroller of  claim 1  wherein the memory device can reside on-chip or off-chip.  
     
     
         3 . The microcontroller of  claim 1  wherein the mechanism includes a trace extractor module.  
     
     
         4 . The microcontroller of  claim 3  wherein the trace extractor module includes a plurality of debug registers which can be configured to determine the behavior of the mechanism.  
     
     
         5 . The microcontroller of  claim 4  wherein the plurality of registers includes a first register (RWA), reflecting the next system memory address to be written; a second register collecting frames into bus-sized units; a third register (CNT) for storing the size of the trace buffer; a fourth register (control) for indicating the actions taken when the trace buffer is full; and a plurality of status registers, wherein each of the plurality of status registers are single-bit read-only registers indicating the status of the trace buffer.  
     
     
         6 . The microcontroller of  claim 1  which further includes: 
 an on-chip debug control in communication with low speed debug port and the microprocessor;    a bus monitor coupled to the on-chip debug control, the address bus and data bus;    a frame buffer in communication with the bus monitor;    a trace extractor module in communication with the frame buffer, on-chip debug control and bus monitor;    a memory interface in communication with the trace extractor module; and    a bus matrix coupled to the memory interface and for communicating with the system memory;    a trace buffer protection module in communication with the on-chip debut control, trace extractor module, and the bus matrix.    
     
     
         7 . The microcontroller of  claim 6  wherein the trace extractor module comprises: 
 a first register (RWD) for receiving data from the frame buffer in bus-sized units; and providing data to the memory interface;    a second register (CNT) which provides the size of the trace buffer and communicates that data to the trace buffer;    a third register for providing the next memory address to be written;    a fourth register for indicating actions to be taken when the trace buffer is full; and    a plurality of status registers.    
     
     
         8 . The microcontroller of  claim 6  wherein the comparator module comprises: 
 a comparator identifying illegal CPU access to system memory locations within the trace buffer; and    a breakpoint generator for halting the CPU when an illegal access id detected.    
     
     
         9 . The microcontroller of  claim 8  wherein a status bit identifies a breakpoint due to illegal access to the trace buffer.  
     
     
         10 . A method for storing and extracting trace information in a microcontroller, the microcontroller comprising a microprocessor, a memory device accessible through a data bus and an address bus coupled to the microprocessor, on-chip debug logic coupled to the microprocessor, the method comprising: 
 accumulating trace frames into a first register until the first register is full;    providing the contents of the first register to the memory device after the first register is full; and    reading out of the memory device the valid trace frames using a debug port.    
     
     
         11 . The method of  claim 10  wherein the valid trace frames are within a trace buffer.  
     
     
         12 . The method of  claim 11  wherein trace buffer is implemented as a circular buffer, thus repeatedly overwritten by new trace frames until the end of the trace capture sequence.  
     
     
         13 . The method of  claim 11  wherein a status register indicates that the trace buffer has been overwritten at least one.  
     
     
         14 . The method of  claim 11  wherein the trace capture sequence ends when the trace buffer is full.  
     
     
         15 . The method of  claim 14  wherein the CPU receives a breakpoint when the trace capture sequence ends.  
     
     
         16 . The method of  claim 15  wherein a status bit identifies the breakpoint issued due to the trace buffer being full.