Method for production of contacts on a wafer

Abstract

The invention relates to a method for production of contacts on a wafer, preferably with the aid of a lithographic process. The preferred embodiment provides a method which overcomes the disadvantages of the complex point/hole lithography process, and which avoids any increase in the process complexity. This method is achieved in that a strip structure extending over two layers is used to structure the contacts. The strip structure in the first layer is rotated at a predetermined angle with respect to the strip structure in the second layer, and the contacts are formed in the mutually overlapping areas of the strip structures in the two layers.

1 . A method for producing contacts on a wafer, the method comprising: 
 providing a first strip structure of a first layer that overlies a second strip structure of a second layer, wherein the first strip structure is rotated at a predetermined angle with respect to the second strip structure; and    forming contacts in mutually overlapping areas of the first strip structure and the second strip structure by using the first strip structure as a mask to etch portions of the second strip structure that do not underlie the first strip structure.    
   
   
       2 . The method of  claim 1 , wherein the contacts are formed without the use of any plug/hole mask.  
   
   
       3 . The method of  claim 1 , wherein the first and second strip structures are formed by means of a lithographic process using a first and a second exposure mask, wherein each exposure mask has a parallel strip structure.  
   
   
       4 . The method of  claim 1 , wherein the predetermined angle is a 45 degree angle.  
   
   
       5 . The method of  claim 1 , wherein at least one of the first strip structure and/or second strip structure is corrugated in selected areas.  
   
   
       6 . The method of  claim 1 , wherein the first and second strip structures are provided with corrections that are predetermined by a chip design in selected areas of a layer.  
   
   
       7 . The method of  claim 1 , wherein the first strip structure comprises a plurality of parallel strips wherein the second strip structure comprises a plurality of parallel strips.  
   
   
       8 . The method of  claim 7 , wherein the first strip structure has a different distance between one strip center and an adjacent strip center than a distance between one strip center and an adjacent strip center of the second strip structure.  
   
   
       9 . The method of  claim 8 , wherein a width of the strips in the first strip structure is the same as a width of the strips in the second strip structure and wherein a space between the strips of the first strip structure is different than a space between the strips of the second strip structure.  
   
   
       10 . The method of  claim 9 , wherein the space between the strips of the first strip structure is greater than the space between the strips of the second strip structure.  
   
   
       11 . The method of  claim 1 , wherein forming the contacts comprises over-etching regions between strips in the second layer.  
   
   
       12 . The method of  claim 11 , wherein the M0 metallization layer forms a row line for memory cells arranged in a same row.  
   
   
       13 . A method of making a semiconductor device, the method comprising: 
 forming a plurality of memory cells in a checkerboard pattern, each memory cell including a contact region;    forming a plurality of conductive lines, each conductive line in the first plurality electrically coupling the contact region of each memory cell along a diagonal line of the checkerboard pattern;    forming a second plurality of conductive lines over the first plurality, each conductive line of the second plurality overlying a row of the memory cells;    using the second plurality of conductive lines as a mask, etching exposed portions of the first plurality of conductive lines such that for each row, the contact regions of that row are coupled together by an associated one of the conductive lines of the second plurality, the associated conductive line being coupled to the contact region by remaining portions of the first plurality of conductive lines.    
   
   
       14 . The method of  claim 13 , wherein forming conductive lines comprises forming trenches.  
   
   
       15 . The method of  claim 13 , wherein the memory cells comprises dynamic random access memory (DRAM) cells.  
   
   
       16 . The method of  claim 15 , wherein the contact region comprises a bitline contact region.  
   
   
       17 . The method of  claim 13 , wherein the second plurality of conductive lines extend at a 45 degree angle with respect to the first plurality of conductive lines.  
   
   
       18 . The method of  claim 13 , wherein the first plurality of conductive lines has a first pitch and the second plurality of conductive lines has a second pitch that is different than the first pitch.  
   
   
       19 . The method of  claim 13 , wherein the second plurality of conductive lines comprises a plurality of corrugated lines.  
   
   
       20 . The method of  claim 13 , wherein the second plurality of conductive lines is formed in an M0 metallization layer.