Semiconductor device and method for fabricating the same

Abstract

A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.

1 - 5 . (canceled)  
   
   
       6 . A method for fabricating a semiconductor device, comprising: 
 the step (a) of sequentially forming a gate insulating film and a gate electrode on a semiconductor layer of a first conductivity type;    the step (b) of forming sidewalls on side surfaces of the gate electrode;    the step (c) of subjecting the semiconductor layer to ion implantation of a first impurity of the first conductivity type using the gate electrode and the sidewalls as a mask, thereby forming impurity implanted layers of the first conductivity type in regions of the semiconductor layer located below sides of the sidewalls;    the step (d) of subjecting the semiconductor layer to ion implantation of a second impurity of a second conductivity type using the gate electrode and the sidewalls as a mask, thereby forming implanted source and drain layers of the second conductivity type in regions of the semiconductor layer located below the sides of the sidewalls; and    the step (e) of subjecting, after the steps (c) and (d), the semiconductor layer to a first thermal treatment, thereby diffusing the second impurity to form diffused source and drain layers of the second conductivity type in regions of the semiconductor layer located below the sides of the sidewalls,    wherein in the step (e), insides of the diffused source and drain layers are formed with impurity implanted regions of the first conductivity type, respectively, which are made by diffusing the first impurity with a lower impurity concentration than that of the diffused source and drain layers.    
   
   
       7 . The method of  claim 6 , further comprising, after the step (a) and before the step (b), 
 the step (f) of subjecting the semiconductor layer to ion implantation of a third impurity of the second conductivity type using the gate electrode as a mask, thereby forming implanted extension layers of the second conductivity type in regions of the semiconductor layer located below sides of the gate electrode,    the step (g) of subjecting the semiconductor layer to ion implantation of a fourth impurity of the first conductivity type using the gate electrode as a mask, thereby forming implanted pocket layers of the first conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and    the step (h) of subjecting, after the steps (f) and (g), the semiconductor layer to a second thermal treatment, thereby diffusing the third impurity to form diffused extension layers of the second conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and simultaneously diffusing the fourth impurity to form diffused pocket layers of the first conductivity type in regions of the semiconductor layer located below the diffused extension layers,    wherein the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer.    
   
   
       8 . The method of  claim 6 , further comprising, before the step (a), the step (i) of subjecting the semiconductor layer to ion implantation of a fifth impurity of the first conductivity type to form an implanted channel layer of the first conductivity type in the semiconductor layer, and then subjecting the semiconductor layer to a third thermal treatment, thereby diffusing the fifth impurity to form a diffused channel layer of the first conductivity type in the semiconductor layer, 
 wherein the impurity concentration of the impurity implanted region is higher than that of the diffused channel layer.    
   
   
       9 . The method of  claim 6 , further comprising, after the step (b) and before the steps (c) and (d), the step (j) of subjecting the semiconductor layer to ion implantation of a sixth impurity using the gate electrode and the sidewalls as a mask, thereby forming amorphous layers in regions of the semiconductor layer located below sides of the sidewalls.  
   
   
       10 . The method of  claim 9 , 
 wherein the sixth impurity is a group IV element.    
   
   
       11 . The method of  claim 6 , 
 wherein ion implantation of the second impurity is conducted at an implantation projected range equal to or larger than the implantation projected range of the first impurity.    
   
   
       12 . The method of  claim 6 , 
 wherein the first impurity is indium.    
   
   
       13 . The method of  claim 6 , further comprising, after the step (d) and before the step (e), the step (k) of performing an extremely low-temperature thermal treatment of a level at which the implanted impurity does not diffuse, thereby restoring crystal damages due to the ion implantation.  
   
   
       14 . The method of  claim 13 , 
 wherein the heating temperature of the extremely low-temperature thermal treatment in the step (k) is from 400 to 700° C. inclusive.    
   
   
       15 . The method of  claim 6 , further comprising: 
 the step (l) of removing, after the step (e), the sidewalls and then subjecting the semiconductor layer to ion implantation of a third impurity of the second conductivity type using the gate electrode as a mask, thereby forming implanted extension layers of the second conductivity type in regions of the semiconductor layer located below sides of the gate electrode;    the step (m) of subjecting the semiconductor layer to ion implantation of a fourth impurity of the first conductivity type using the gate electrode as a mask, thereby forming implanted pocket layers of the first conductivity type in regions of the semiconductor layer located below the sides of the gate electrode; and    the step (n) of subjecting, after the steps (l) and (m), the semiconductor layer to a second thermal treatment, thereby diffusing the third impurity to form diffused extension layers of the second conductivity type in regions of the semiconductor layer located below the sides of the gate electrode, and simultaneously diffusing the fourth impurity to form diffused pocket layers of the first conductivity type in regions of the semiconductor layer located below the diffused extension layers,    wherein the impurity concentration of the impurity implanted region is higher than that of the diffused pocket layer.    
   
   
       16 . The method of  claim 9 , 
 wherein in the step (j), the sixth impurity is implanted by angled implantation having a predetermined angle with respect to the normal to a main surface of the semiconductor layer.