US2006275932A1PendingUtilityA1
Semiconductor device, function setting method thereof, and evaluation method thereof
Assignee: MATSUSHITA ELECTRIC INDUSTRIAL CO LTDPriority: Oct 5, 2000Filed: Aug 1, 2006Published: Dec 7, 2006
Est. expiryOct 5, 2020(expired)· nominal 20-yr term from priority
H10W 70/63H10W 46/601H10W 46/403H10W 46/00H10W 70/641H10W 70/611G06F 30/30G06F 15/7867Y02D10/00
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Claims
Abstract
The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.
Claims
exact text as granted — not AI-modified1 - 28 . (canceled)
29 . A method for evaluating a semiconductor device, comprising:
a step (a) of mounting, by lamination on a semiconductor circuit board having a wiring layer, a plurality of evaluation chip IPs each having at least one function; and a step (b) of evaluating said at least one function of the evaluation chips by simulation.
30 . The method for evaluating a semiconductor device according to claim 29 ,
wherein step (b) is performed by displaying internal documentation storing the function of the chip IPs on a display device.
31 . The method for evaluating a semiconductor device according to claim 29 ,
wherein in step (a), the wiring layer of the semiconductor wiring circuit is formed separated into a normal operation wiring layer and an evaluation wiring layer above the normal operation wiring layer; and the method further includes a step of removing the evaluation wiring layer from the semiconductor circuit board and leaving the normal operation wiring layer, which is performed after step (b).
32 . A method for evaluating a semiconductor device comprising a semiconductor circuit board having a wiring layer, and a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board;
wherein a connection test is performed by exchanging information between corresponding terminals among the plurality of chip IPs.
33 . A method for function setting of a semiconductor device comprising a semiconductor circuit board having a wiring layer, and a chip IP that is mounted by lamination on the semiconductor circuit board and that has a plurality of functions;
wherein settings are performed such that only a portion of the plurality of functions are activated.
34 . The method for function setting of a semiconductor device in accordance with claim 33 ,
wherein only said portion of functions is activated by locking a wiring layout of the wiring layer.
35 . The method for function setting of a semiconductor device in accordance with claim 34 ,
wherein only said portion of functions is activated by locking a logic input supplied to the plurality of functions.
36 . The method for function setting of a semiconductor device in accordance with claim 33 ,
wherein only said portion of functions is activated by allowing only said portion of functions to be read out.
37 . The method for function setting of a semiconductor device in accordance with claim 33 ,
wherein only said portion of functions is activated by remote control over a network.
38 . The method for function setting of a semiconductor device in accordance with claim 33 ,
wherein only said portion of functions is activated by inputting a clock signal only into said portion of functions.
39 . The method for function setting of a semiconductor device in accordance with claim 33 ,
wherein only said portion of functions is activated by supplying a power source voltage only to said portion of functions.
40 . The method for function setting of a semiconductor device in accordance with claim 33 ,
wherein only said portion of functions is activated by supplying an input signal only to said portion of functions.
41 . A method for function setting of a semiconductor device comprising a semiconductor circuit board having a wiring layer, and a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board;
wherein, in accordance with function information of only a portion of the plurality of chip IPs, the functions of the other chip IPs are changed or set.
42 . A method for function setting of a semiconductor device comprising a semiconductor circuit board having a wiring layer, a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board and that each have a plurality of functions, and function information storage means provided on each of the chip IPs that is for storing function information relating to said plurality of functions;
wherein, based on the function information of only a portion of the plurality of chip IPs, the functions of the other chip IPs are changed or set.Join the waitlist — get patent alerts
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