DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators

Abstract

Methods for operating structures and systems having memory cells with a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.

1 . A method comprising: 
 operating a memory adapted to control a memory cell in a volatile memory mode and in a non-volatile memory mode, the memory cell including: 
 a source region and a drain region separated by a channel region in a substrate;  
 a storage capacitor coupled to one of the source and drain regions;  
 a floating gate opposing the channel region;  
 a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;  
 a control gate opposing the floating gate; and  
 a metal oxide insulator separating the control gate from the floating gate, the metal oxide insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height;  
   sensing a first charge representing a data value from the storage capacitor if the memory operates the memory cell in the volatile memory mode; and    sensing a second charge representing a data value from the floating gate if the memory operates the memory cell in the volatile memory mode.    
   
   
       2 . The method of  claim 1 , wherein the method further includes writing to the floating gate using channel hot electron injection.  
   
   
       3 . The method of  claim 2 , wherein writing to the floating gate using channel hot electron injection includes: 
 applying a large voltage to the control gate; and    applying a large voltage to the drain region.    
   
   
       4 . The method of  claim 1 , wherein the method further includes writing to the floating gate by tunneling electrons from the control gate to the floating gate.  
   
   
       5 . The method of  claim 4 , wherein writing to the floating gate by tunneling electrons from the control gate to the floating gate includes: 
 applying a positive voltage to the substrate; and    applying a large negative voltage to the control gate.    
   
   
       6 . The method of  claim 1 , wherein the method further includes erasing charge from the floating gate by tunneling electrons from the floating gate to the control gate.  
   
   
       7 . The method of  claim 6 , wherein erasing charge from the floating gate by tunneling electrons from the floating gate to the control gate includes: 
 providing a negative voltage to the substrate; and    providing a large positive voltage to the control gate.    
   
   
       8 . The method of  claim 6 , wherein tunneling electrons from the floating gate to the control gate includes tunneling electrons from a first metal layer formed on the floating gate through the metal oxide insulator to a second metal layer formed on the control gate, the first metal layer in contact with the metal oxide insulator and the second metal layer in contact with the metal oxide insulator.  
   
   
       9 . The method of  claim 1 , wherein the method further includes reading the memory cell in the non-volatile memory mode by: 
 applying a positive voltage to the control gate of the memory cell; and    sensing a current from the drain region.    
   
   
       10 . The method of  claim 1 , wherein operating the memory to control the memory cell in the volatile memory mode includes reading charge from the capacitor of the memory cell, writing charge to the capacitor of the memory cell, or reading charge from the capacitor of the memory cell and writing charge to the capacitor of the memory cell.  
   
   
       11 . A method comprising: 
 operating a memory adapted to control a memory cell in a volatile memory mode and in a non-volatile memory mode, the memory cell including: 
 a source region and a drain region separated by a channel region in a substrate;  
 a storage capacitor coupled to the drain region;  
 a polysilicon floating gate opposing the channel region, the polysilicon floating gate having a metal layer disposed thereon;  
 a silicon oxide layer separating the floating gate from the channel region, the silicon oxide layer having a tunneling barrier height of about 3.2 eV;  
 a metal oxide insulator, the metal oxide insulator having a tunneling barrier height being less than the tunneling barrier height of the silicon oxide layer, the metal oxide insulator in contact with the metal layer disposed on the polysilicon floating gate; and  
 a control gate opposing the floating gate and separated from the floating gate by the metal oxide insulator;  
   sensing a first charge representing a data value from the storage capacitor if the memory operates the memory cell in the volatile memory mode; and    sensing a second charge representing a data value from the floating gate if the memory operates the memory cell in the volatile memory mode.    
   
   
       12 . The method of  claim 1 , wherein the method further includes writing to the floating gate using channel hot electron injection.  
   
   
       13 . The method of  claim 12 , wherein writing to the floating gate using channel hot electron injection includes: 
 applying a large voltage to the control gate; and    applying a large voltage to the drain region.    
   
   
       14 . The method of  claim 1 , wherein the method further includes writing to the floating gate by tunneling electrons from the control gate to the floating gate.  
   
   
       15 . The method of  claim 14 , wherein writing to the floating gate by tunneling electrons from the control gate to the floating gate includes: 
 applying a positive voltage to the substrate; and    applying a large negative voltage to the control gate.    
   
   
       16 . The method of  claim 1 , wherein the method further includes erasing charge from the floating gate by tunneling electrons from the floating gate to the control gate.  
   
   
       17 . The method of  claim 16 , wherein erasing charge from the floating gate by tunneling electrons from the floating gate to the control gate includes: 
 providing a negative voltage to the substrate; and    providing a large positive voltage to the control gate.    
   
   
       18 . The method of  claim 16 , wherein tunneling electrons from the floating gate to the control gate includes tunneling electrons from the metal layer disposed on the floating gate through the metal oxide insulator to a metal layer disposed on the control gate, the metal layer disposed on the control gate in contact with the metal oxide insulator, the control gate including polysilicon.  
   
   
       19 . The method of  claim 1 , wherein the method further includes reading the memory cell in the non-volatile memory mode by: 
 applying a positive voltage to the control gate of the memory cell; and    sensing a current from the drain region.    
   
   
       20 . The method of  claim 1 , wherein operating the memory to control the memory cell in the volatile memory mode includes reading charge from the capacitor of the memory cell, writing charge to the capacitor of the memory cell, or reading charge from the capacitor of the memory cell and writing charge to the capacitor of the memory cell.