Semiconductor device and method of manufacturing same

Abstract

A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film ( 6 ) is formed partially on the upper surface of a silicon layer ( 3 ). A gate electrode ( 7 ) of polysilicon is formed partially on the silicon oxide film ( 6 ). A portion of the silicon oxide film ( 6 ) underlying the gate electrode ( 7 ) functions as a gate insulation film. A silicon nitride film ( 9 ) is formed on each side surface of the gate electrode ( 7 ), with a silicon oxide film ( 8 ) therebetween. The silicon oxide film ( 8 ) and the silicon nitride film ( 9 ) are formed on the silicon oxide film ( 6 ). The width (W 1 ) of the silicon oxide film ( 8 ) in a direction of the gate length is greater than the thickness (T 1 ) of the silicon oxide film ( 6 ).

1 - 12 . (canceled)  
   
   
       13 . A semiconductor device comprising: 
 a substrate;    a semiconductor element including (a) a gate electrode formed on a main surface of said substrate, with a gate insulation film therebetween, and extending in a predetermined direction, (b) a first sidewall formed on a side surface of said gate electrode, (c) a body region formed in said substrate under said gate electrode, and (d) a pair of source/drain regions formed in said substrate, with said body region disposed between said pair of source/drain regions;    an interlayer insulation film formed on said substrate to cover said semiconductor element; and    a gate interconnect line in contact with an upper surface of said gate electrode and extending in said predetermined direction, said gate interconnect line being formed in said interlayer insulation film, wherein a dimension of said gate interconnect line in a direction of gate length of said gate electrode is greater than said gate length of said gate electrode.    
   
   
       14 . The semiconductor device according to  claim 13 , further comprising 
 a second sidewall formed on said side surface of said gate electrode, with said first sidewall therebetween.    
   
   
       15 . The semiconductor device according to  claim 14 , wherein 
 a dimension of said second sidewall in said direction of said gate length is greater than a dimension of said first sidewall in said direction of said gate length.    
   
   
       16 . The semiconductor device according to  claim 13 , further comprising 
 a contact plug connected to said source/drain regions and formed in said interlayer insulation film,    wherein said dimension of said gate interconnect line in said direction of said gate length is less than a dimension of said contact plug in said direction of said gate length.