Transistor with nanocrystalline silicon gate structure

Abstract

A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 100 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

1 . A memory cell, comprising: 
 a source region;    a drain region;    a channel region located between the source region and the drain region;    a control gate located over the channel region;    a floating gate located between the control gate and the channel region and separated from both the control gate and the channel region by insulator portions, the floating gate including: 
 a plurality of nanocrystalline silicon particles in physical and electrical contact with each other; and  
 wherein the nanocrystalline silicon particles are embedded in one of the insulator portions.  
   
   
   
       2 . The memory cell of  claim 1 , wherein the nanocrystalline silicon particles have a general diameter of approximately 10 Å to 100 Å.  
   
   
       3 . The memory cell of  claim 1 , wherein the insulator portions include a first insulator layer and a second insulator layer and at least one insulator layer includes silicon oxide.  
   
   
       4 . The memory cell of  claim 1 , wherein the nanocrystalline silicon particles are conductively doped.  
   
   
       5 . The memory cell of  claim 5 , wherein the gate insulator portion between the floating gate and the channel region is thicker than 20 Å.  
   
   
       6 . A memory cell, comprising: 
 a source region;    a drain region;    a channel region located between the source region and the drain region;    a control gate located over the channel region;    a floating gate located between the control gate and the channel region and separated from both the control gate and the channel region by insulator portions, the floating gate including a plurality of nanocrystalline silicon particles embedded between the insulator portions; and    wherein the floating gate is configured to share a common charge in a plane substantially parallel to the channel region.    
   
   
       7 . The flash memory cell of  claim 6 , wherein the nanocrystalline silicon particles have a general diameter of approximately 10 Å to 100 Å.  
   
   
       8 . The memory cell of  claim 6 , wherein the nanocrystalline silicon particles are conductively doped.  
   
   
       9 . A memory cell, comprising: 
 a source region;    a drain region;    a channel region located between the source region and the drain region;    a control gate located over the channel region;    a floating gate located between the control gate and the channel region and separated from both the control gate and the channel region by insulator portions, the floating gate having a lower electron affinity than a polysilicon gate, the floating gate including a plurality of nanocrystalline silicon particles in physical and electrical contact with each other.    
   
   
       10 . The memory cell of  claim 9 , wherein the nanocrystalline silicon particles have a general diameter of approximately 10 Å to 100 Å.  
   
   
       11 . The memory cell of  claim 9 , wherein the control circuitry is configured to utilize Fowler-Nordheim tunneling mechanisms to store data on the gate.  
   
   
       12 . A flash memory device, comprising: 
 an array of memory cells, the cells including: 
 a source region;  
 a drain region;  
 a channel region located between the source region and the drain region;  
 a gate, including: 
 a plurality of nanocrystalline silicon particles in physical contact and in electrical contact with each other;  
 wherein the nanocrystalline silicon particles are at least partially embedded in an insulator layer;  
 a gate insulator separating the gate from the channel region; and  
 
   control circuitry to select cells in the array of memory cells.    
   
   
       13 . The flash memory device of  claim 12 , wherein the nanocrystalline silicon particles have a general diameter of approximately 10 Å to 100 Å.  
   
   
       14 . The flash memory device of  claim 12 , wherein the gate insulator is thicker than 20 Å.  
   
   
       15 . The flash memory device of  claim 14 , wherein the control circuitry is configured to utilize Fowler-Nordheim tunneling mechanisms to store data on the gate.  
   
   
       16 . A flash memory device, comprising: 
 an array of memory cells, the cells including: 
 a source region;  
 a drain region;  
 a channel region located between the source region and the drain region;  
 a gate, including a plurality of nanocrystalline silicon particles in an insulator layer configured to allow a shared common charge in a plane substantially parallel to the channel region;  
 a gate insulator separating the gate from the channel region; and  
   control circuitry to select cells in the array of memory cells.    
   
   
       17 . The flash memory device of  claim 16 , wherein the plurality of nanocrystalline silicon particles includes clusters of nanocrystalline particles.  
   
   
       18 . The flash memory device of  claim 16 , wherein the nanocrystalline silicon particles are conductively doped.  
   
   
       19 . An electronic system, comprising: 
 a flash memory, wherein memory cells in the flash memory include: 
 a source region;  
 a drain region;  
 a channel region located between the source region and the drain region;  
 a gate having a lower electron affinity than a polysilicon gate, the gate including a plurality of nanocrystalline silicon particles in physical contact and in electrical contact with each other;  
 a gate insulator separating the gate from the channel region; and  
   a processor coupled to the flash memory to process data stored in the flash memory.    
   
   
       20 . The electronic system of  claim 19 , wherein the control circuitry is configured to utilize Fowler-Nordheim tunneling mechanisms to store data on the gate.  
   
   
       21 . The electronic system of  claim 19 , wherein the gate insulator includes silicon oxide.  
   
   
       22 . The electronic system of  claim 19 , wherein the nanocrystalline silicon particles are conductively doped.