Semiconductor device
Abstract
An active area ( 1 ) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film ( 7 ) encloses this active area. A gate electrode ( 30 ) is arranged on a depressed region (DR) having an edge portion which is located on a low position due to the concave part, while a gate electrode ( 20 ) is arranged on an ordinary region (OR) having an edge portion projecting beyond the depressed region. A gate end cap (margin part) of the gate electrode ( 20 ) has a length x, while that of the gate electrode ( 30 ) has a length x+α. Thus provided is a semiconductor device causing no current defect between source/drain regions even if the active area and an insulating film defining this active area fail to satisfy the layout design following refinement of the semiconductor device.
Claims
exact text as granted — not AI-modified1 . A semiconductor device comprising:
an active area being provided with at least one MOS transistor; and an insulating film defining said active area, wherein said active area is set in a shape having a concave part in a shape along a plan view, said active area is provided with: an ordinary region, and a depressed region having an edge portion being depressed beyond said ordinary region due to presence of said concave part, said at least one MOS transistor includes: a plurality of MOS transistors being arranged on said depressed region and electrically connected in parallel with each other, and respective gate electrodes of said plurality of MOS transistors are arranged in parallel with each other and electrically connected in common, so that margin parts of at least a gate electrode being located most approximately to said ordinary region and that adjacent to said gate electrode are connected with each other among said respective gate electrodes of said plurality of MOS transistors.
2 . The semiconductor device in accordance with claim 1 , wherein all margin parts of said respective gate electrodes of said plurality of MOS transistors are connected with each other.Join the waitlist — get patent alerts
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