Transistors having a recessed channel region and methods of fabricating the same

Abstract

A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

1 . A method of fabricating a transistor, comprising: 
 forming a device isolation layer on a substrate to define an active region;    forming an insulation pattern on a sidewall of the device isolation layer opposite to the active region;    etching the active region using the insulation pattern and the device isolation layer as an etch mask to form a recess region;    removing the insulation pattern;    forming a gate insulation layer on the active region including the recess region; and    forming a gate pattern on the gate insulation layer, the gate pattern crossing over the active region including the recess region.    
     
     
         2 . The method of  claim 1 , wherein forming the insulation pattern comprises: 
 conformally forming a spacer insulation layer on a surface of the substrate where the device isolation layer is formed; and    anisotropically etching the spacer insulation layer to form a spacer insulation pattern on the sidewall of the device isolation layer opposite to the active region.    
     
     
         3 . The method of  claim 1 , wherein forming the device isolation layer and forming the insulation pattern comprises: 
 forming a hard mask pattern on a substrate;    etching the substrate using the hard mask pattern as an etch mask to form a trench region;    forming a device isolation layer to fill the trench region; and    etching the hard mask pattern at a central portion of the active region in parallel with the active region to expose the central portion of the active region and to form an insulation pattern on the sidewall of the device isolation layer.    
     
     
         4 . A method of fabricating a transistor, comprising: 
 forming a device isolation layer on a substrate to define an active region;    forming a recess region in the active region;    forming a gate insulation layer on the active region including the recess region;    forming a gate pattern on the gate insulation layer, the gate pattern crossing over the active region including the recess region; and    forming source and drain regions in the active region adjacent to respective sides of the gate pattern.    
     
     
         5 . The method of  claim 4 , wherein forming the recess region comprises: 
 forming a mask pattern having an opening exposing a portion of the active region;    etching a portion of the active region using the mask pattern as an etch mask to form the recess region; and    removing the mask pattern.    
     
     
         6 . The method of  claim 4 , wherein forming the recess region comprises: 
 forming a spacer pattern on a sidewall of the device isolation layer facing the active region;    etching a portion of the active region using the device isolation layer and the spacer as an etch mask;    removing the spacer pattern;    forming a mask pattern having an opening exposing a portion of the active region, the mask pattern crossing over the active region;    etching a portion of the active region using the mask pattern as an etch mask; and    removing the mask pattern.    
     
     
         7 . The method of  claim 6 , further comprising: 
 removing the spacer pattern after removing the mask pattern.    
     
     
         8 . The method of  claim 6 , further comprising: 
 removing the spacer pattern before removing the mask pattern.