Method for forming a MOS transistor and structure thereof

Abstract

A method for forming a MOS transistor having LDD structure by a simple and a few number of processes and a structure thereof are described. In accordance with the present invention, a low concentration of an impurity region can be formed in a semiconductor film part between an end of gate electrode and source or drain, by forming an ordinary gate insulating film extending beyond the gate electrode in the direction along the source and drain, in place of a spacer in the side of gate electrode which has been required for a preparation of conventional TFT having LDD structure, and further by forming a thinner insulating film than the gate insulating film in the side thereof, and by utilizing the thickness difference between the gate insulating film part excepting the gate electrode and the thin insulating film in the side thereof.

1 . A semiconductor device comprising: 
 a substrate;    a semiconductor layer formed over said substrate, said semiconductor layer including source and drain regions, a channel region and first and second LDD regions formed between said channel region and said source and drain regions;    a gate insulating film formed over said semiconductor layer, said gate insulating film having a first portion which completely covers said channel region and second portions wherein said second portions have a smaller thickness than the first portion;    a gate electrode formed over said channel region with said first portion of the gate insulating film interposed therebetween wherein said first portion extends beyond side edges of the gate electrode to cover said first and second LDD regions,    wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said substrate.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein said impurity comprises at least one of phosphorus and boron.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein said gate electrode comprises a doped polysilicon.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein said gate insulating film has plural layers.  
   
   
       6 . An active matrix display device including a thin film transistor, comprising: 
 a glass substrate;    a semiconductor layer formed over said glass substrate, said semiconductor layer including source and drain regions, a channel region and first and second LDD regions formed between said channel region and said source and drain regions;    a gate insulating film formed over said semiconductor layer, said gate insulating film having a first portion which completely covers said channel region and second portions wherein said second portions have a smaller thickness than the first portion;    a gate electrode formed over said channel region with said first portion of the gate insulating film interposed therebetween wherein said first portion extends beyond side edges of the gate electrode to cover said first and second LDD regions,    wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said glass substrate.    
   
   
       7 . The active matrix display device according to  claim 6 , wherein said impurity comprises at least one of phosphorus and boron.  
   
   
       8 . The active matrix display device according to  claim 6 , wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.  
   
   
       9 . The active matrix display device according to  claim 6 , wherein said gate electrode comprises a doped polysilicon.  
   
   
       10 . The active matrix display device according to  claim 6 , wherein said gate insulating film has plural layers.  
   
   
       11 . A semiconductor device comprising: 
 a substrate;    a semiconductor layer formed over said substrate, said semiconductor layer including source and drain regions, a channel region and first and second LDD regions formed between said channel region and said source and drain regions;    a gate insulating film formed over said semiconductor layer, said gate insulating film having a first portion which completely covers said channel region and second portions wherein said second portions have a smaller thickness than the first portion;    a gate electrode formed over said channel region with said first portion of the gate insulating film interposed therebetween wherein said first portion extends beyond side edges of the gate electrode to cover said first and second LDD regions,    wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said substrate, and    wherein a width of said first LDD region is substantially the same as a width of said second LDD region.    
   
   
       12 . The semiconductor device according to  claim 11 , wherein said impurity comprises at least one of phosphorus and boron.  
   
   
       13 . The semiconductor device according to  claim 11 , wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.  
   
   
       14 . The semiconductor device according to  claim 11 , wherein said gate electrode comprises a doped polysilicon.  
   
   
       15 . The semiconductor device according to  claim 11 , wherein said gate insulating film has plural layers.  
   
   
       16 . An active matrix display device including a thin film transistor, comprising: 
 a glass substrate;    a semiconductor layer formed over said glass substrate, said semiconductor layer including source and drain regions, a channel region and first and second LDD regions formed between said channel region and said source and drain regions;    a gate insulating film formed over said semiconductor layer, said gate insulating film having a first portion which completely covers said channel region and second portions wherein said second portions have a smaller thickness than the first portion;    a gate electrode formed over said channel region with said first portion of the gate insulating film interposed therebetween wherein said first portion extends beyond side edges of the gate electrode to cover said first and second LDD regions,    wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said glass substrate, and    wherein a width of said first LDD region is substantially the same as a width of said second LDD region.    
   
   
       17 . The active matrix display device according to  claim 16 , wherein said impurity comprises at least one of phosphorus and boron.  
   
   
       18 . The active matrix display device according to  claim 16 , wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.  
   
   
       19 . The active matrix display device according to  claim 16 , wherein said gate electrode comprises a doped polysilicon.  
   
   
       20 . The active matrix display device according to  claim 16 , wherein said gate insulating film has plural layers.  
   
   
       21 . A semiconductor device comprising: 
 a substrate;    a semiconductor layer formed over said substrate, said semiconductor layer including source and drain regions, a channel region and first and second LDD regions formed between said channel region and said source and drain regions wherein each of said source and drain regions has a tapered side edge;    a gate insulating film formed over said semiconductor layer, said gate insulating film having a first portion which completely covers said channel region and second portions wherein said second portions have a smaller thickness than the first portion;    a gate electrode formed over said channel region with said first portion of the gate insulating film interposed therebetween wherein said first portion extends beyond side edges of the gate electrode to cover said first and second LDD regions,    wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said substrate, and    wherein a width of said first LDD region is substantially the same as a width of said second LDD region.    
   
   
       22 . The semiconductor device according to  claim 21 , wherein said impurity comprises at least one of phosphorus and boron.  
   
   
       23 . The semiconductor device according to  claim 21 , wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.  
   
   
       24 . The semiconductor device according to  claim 21 , wherein said gate electrode comprises a doped polysilicon.  
   
   
       25 . The semiconductor device according to  claim 21 , wherein said gate insulating film has plural layers.  
   
   
       26 . An active matrix display device including a thin film transistor, comprising: 
 a glass substrate;    a semiconductor layer formed over said glass substrate, said semiconductor layer including source and drain regions, a channel region and first and second LDD regions formed between said channel region and said source and drain regions wherein each of said source and drain regions has a tapered side edge;    a gate insulating film formed over said semiconductor layer, said gate insulating film having a first portion which completely covers said channel region and second portions wherein said second portions have a smaller thickness than the first portion;    a gate electrode formed over said channel region with said first portion of the gate insulating film interposed therebetween wherein said first portion extends beyond side edges of the gate electrode to cover said first and second LDD regions,    wherein a concentration of an impurity contained in said source and drain regions monotonically decreases in a thickness direction of the semiconductor layer at least partly toward said glass substrate, and    wherein a width of said first LDD region is substantially the same as a width of said second LDD region.    
   
   
       27 . The active matrix display device according to  claim 26 , wherein said impurity comprises at least one of phosphorus and boron.  
   
   
       28 . The active matrix display device according to  claim 26 , wherein said first and second LDD regions contain said impurity at a concentration lower than said source and drain regions.  
   
   
       29 . The active matrix display device according to  claim 26 , wherein said gate electrode comprises a doped polysilicon.  
   
   
       30 . The active matrix display device according to  claim 26 , wherein said gate insulating film has plural layers.